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Received-SPF: SoftFail (protection.outlook.com: domain of transitioning amd.com discourages use of 149.199.90.133 as permitted sender) Received: from satlexmb07.amd.com (149.199.90.133) by BN3PEPF00022BBA.mail.protection.outlook.com (10.167.248.116) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.360.3 via Frontend Transport; Wed, 26 Aug 2026 22:37:10 +0000 Received: from dryer.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Wed, 26 Aug 2026 17:37:09 -0500 From: Kim Phillips To: , , , CC: Sean Christopherson , Paolo Bonzini , K Prateek Nayak , "Nikunj A Dadhania" , Tom Lendacky , "Michael Roth" , Borislav Petkov , Borislav Petkov , Naveen Rao , David Kaplan , Pawan Gupta , "Dave Hansen" , Kim Phillips , Nathan Fontenot Subject: [PATCH v5 8/8] KVM: SEV: Add support for SNP BTB Isolation Date: Wed, 26 Aug 2026 17:35:10 -0500 Message-ID: <20260826223510.3669875-9-kim.phillips@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260826223510.3669875-1-kim.phillips@amd.com> References: <20260826223510.3669875-1-kim.phillips@amd.com> Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF00022BBA:EE_|SA5PPF7D510B798:EE_ X-MS-Office365-Filtering-Correlation-Id: 42cb55a5-6f07-463d-99c0-08df03c2916c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|376014|1800799024|23010399003|82310400026|10067099003|56012099006|5023799004|11063799006|6133799003|3023799007|22082099003|18002099003; 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BTB Isolation is an optional feature that can be enabled by the guest to ensure its guest Branch Target Buffers (BTBs) are not affected by any context outside that guest. SNP-active guests may choose to enable the Branch Target Buffer Isolation mode through SEV_FEATURES bit 7 (BTBIsolation). Unlike the sibling features advertised here (Secure TSC, IBPB-on-Entry), BTB Isolation is advertised unconditionally. This is deliberate, not an oversight: the AMD64 APM (Vol. 2, Section 15.36.17 "Side-Channel Protection") defines BTB Isolation as architecturally present on every SEV-SNP-capable processor. There is therefore no host enumeration bit for it (no CPUID leaf or MSR capability), by design -- unlike IBPB-on-Entry, whose host support is enumerated via CPUID Fn8000_001F[IbpbOnEntry] bit 31 precisely because it is not universal. A per-feature host gate is thus neither possible nor meaningful; if SNP is supported, BTB Isolation is present. Nor does the guest have to take the host's word for it. SEV_FEATURES is written into the VMSA by sev_es_sync_vmsa() and measured by SNP_LAUNCH_UPDATE with SNP_PAGE_TYPE_VMSA, so bit 7 is covered by the launch measurement and appears in the attestation report. At runtime the guest can additionally read the active state from SEV_STATUS bit 9 (MSR_AMD64_SNP_BTB_ISOLATION, dumped as "BTBIsol" by sev_status_feat_names[] in arch/x86/coco/sev/core.c). A guest requiring BTB Isolation can therefore confirm it is active rather than trusting what the host advertised. Also add SVM_SEV_FEAT_BTB_ISOLATION to the sev_init2 selftest's SNP_ONLY_FEATURES and KNOWN_FEATURES to validate it is accepted for SNP guests and rejected for SEV-ES. For more info, refer to page 615, Section 15.36.17 "Side-Channel Protection", AMD64 Architecture Programmer's Manual Volume 2: System Programming Part 2, Pub. 24593 Rev. 3.42 - March 2024 (see Link). Link: https://bugzilla.kernel.org/attachment.cgi?id=306250 Cc: Sean Christopherson Cc: Borislav Petkov (AMD) Signed-off-by: Kim Phillips Assisted-by: ClaudeCode:claude-opus-4-7 Reviewed-by: Tom Lendacky --- arch/x86/include/asm/svm.h | 2 ++ arch/x86/kvm/svm/sev.c | 8 ++++++++ tools/testing/selftests/kvm/x86/sev_init2_tests.c | 2 ++ 3 files changed, 12 insertions(+) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index 9d8107824d10..0da2234b71c6 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -309,10 +309,12 @@ static_assert((X2AVIC_4K_MAX_PHYSICAL_ID & AVIC_PHYSICAL_MAX_INDEX_MASK) == X2AV #define SVM_SEV_FEAT_RESTRICTED_INJECTION BIT_ULL(3) #define SVM_SEV_FEAT_ALTERNATE_INJECTION BIT_ULL(4) #define SVM_SEV_FEAT_DEBUG_SWAP BIT_ULL(5) +#define SVM_SEV_FEAT_BTB_ISOLATION BIT_ULL(7) #define SVM_SEV_FEAT_SECURE_TSC BIT_ULL(9) #define SVM_SEV_FEAT_IBPB_ON_ENTRY BIT_ULL(21) #define SVM_SEV_FEAT_SNP_ONLY_MASK (SVM_SEV_FEAT_SNP_ACTIVE | \ + SVM_SEV_FEAT_BTB_ISOLATION | \ SVM_SEV_FEAT_SECURE_TSC | \ SVM_SEV_FEAT_IBPB_ON_ENTRY) diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 20a761cf3491..53cc6d043883 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -3260,6 +3260,14 @@ void __init sev_hardware_setup(void) if (sev_snp_enabled) { sev_supported_vmsa_features |= SVM_SEV_FEAT_SNP_ACTIVE; + /* + * Unlike Secure TSC and IBPB-on-Entry below, BTB Isolation has + * no host enumeration bit to gate on: the APM defines it as + * architecturally present on every SEV-SNP-capable processor. + * If SNP is supported, BTB Isolation is available. + */ + sev_supported_vmsa_features |= SVM_SEV_FEAT_BTB_ISOLATION; + if (tsc_khz && cpu_feature_enabled(X86_FEATURE_SNP_SECURE_TSC)) sev_supported_vmsa_features |= SVM_SEV_FEAT_SECURE_TSC; diff --git a/tools/testing/selftests/kvm/x86/sev_init2_tests.c b/tools/testing/selftests/kvm/x86/sev_init2_tests.c index f2f97dca3935..3f592e245a66 100644 --- a/tools/testing/selftests/kvm/x86/sev_init2_tests.c +++ b/tools/testing/selftests/kvm/x86/sev_init2_tests.c @@ -15,11 +15,13 @@ #define SVM_SEV_FEAT_SNP_ACTIVE BIT_ULL(0) #define SVM_SEV_FEAT_DEBUG_SWAP BIT_ULL(5) +#define SVM_SEV_FEAT_BTB_ISOLATION BIT_ULL(7) #define SVM_SEV_FEAT_SECURE_TSC BIT_ULL(9) #define SVM_SEV_FEAT_IBPB_ON_ENTRY BIT_ULL(21) /* Features valid only for SNP guests, rejected for SEV-ES and below. */ #define SNP_ONLY_FEATURES (SVM_SEV_FEAT_SNP_ACTIVE | \ + SVM_SEV_FEAT_BTB_ISOLATION | \ SVM_SEV_FEAT_SECURE_TSC | \ SVM_SEV_FEAT_IBPB_ON_ENTRY) -- 2.43.0