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Mon, 14 Sep 2026 13:46:03 -0700 (PDT) X-Received: by 2002:a17:903:120a:b0:2d8:d4d2:d139 with SMTP id d9443c01a7336-2dd7655bb26mr12602725ad.21.1789418762993; Mon, 14 Sep 2026 13:46:02 -0700 (PDT) Received: from localhost ([50.35.44.179]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33bdd76abcbsm4592622eec.22.2026.09.14.13.46.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2026 13:46:02 -0700 (PDT) Date: Mon, 14 Sep 2026 13:45:59 -0700 From: Jonathan Cameron To: "Aneesh Kumar K.V (Arm)" Cc: linux-coco@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jason Gunthorpe , Catalin Marinas , Greg KH , Jeremy Linton , Jonathan Cameron , Lorenzo Pieralisi , Mark Rutland , Sudeep Holla , Will Deacon , Steven Price , Suzuki K Poulose , Andre Przywara Subject: Re: [PATCH v11 3/7] firmware: arm_rmm: Move RSI support out of arch/arm64 Message-ID: <20260914134559.00004e1b@oss.qualcomm.com> In-Reply-To: <20260914060511.277948-4-aneesh.kumar@kernel.org> References: <20260914060511.277948-1-aneesh.kumar@kernel.org> <20260914060511.277948-4-aneesh.kumar@kernel.org> Organization: Qualcomm X-Mailer: Claws Mail 4.4.0 (GTK 3.24.51; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=CKa/zhrD c=1 sm=1 tr=0 ts=6aa85d0c cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=aNnz9XPx1a4JIXSYt2cE/A==:17 a=kj9zAlcOel0A:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=VwQbUJbxAAAA:8 a=Ikd4Dj_1AAAA:8 a=7CQSdrXTAAAA:8 a=EUspDBNiAAAA:8 a=6n8XPUQpuYwtPrU-WrUA:9 a=CjuIK1q_8ugA:10 a=1OuFwYUASf3TG4hYMiVC:22 a=a-qgeE7W1pNrGK8U0ZQC:22 X-Proofpoint-ORIG-GUID: cPiSp3pzCKYTN8mCNlJCDrkF0cBJevgS X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE0MDI5NiBTYWx0ZWRfXx+NKnL0jmeou 6xLVx5kI8GY0QGYkHC9pc+436imrp6iqYWlJtR26inZElgTcWwBA9/XTJ489SbG+USSbRoEg1bP 2B5Fcl2HzWRvQZ/XNIqjEzOs6x+L09A= X-Proofpoint-GUID: cPiSp3pzCKYTN8mCNlJCDrkF0cBJevgS X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE0MDI5NiBTYWx0ZWRfXzKZHw/ed5QGm z6bSsyjhGNuf9jXC44qN+68d6vmj4mGIaMumIMXsUDBPJF2xgr3zBsrsHaP8fL1PC0T45UqedUr HKzxlDslJktw3asUWRZndbGxfVgEkJy41+jY40xVLbiW3uDz/SQRKe8Muw4sAngnI6D12zFod9k Kfii3XTXcZ8mgvD7fx7BaZF3Ssk2UUiEaToLkftoM8HVF1DPGtnQSM/uoJvKTUjBZZUhjPvoZnE ex7DVwEms/rGZGoH5L/iD/vvy6Vdv/JSrhf2p4mHljQiLLdoH44+pq+IWeyv6DI5OLcv2xpc4SS Amf8FLvYTTMXcnm04Pm5kOQFlo3za1j+KL4ikisMUd9xl5iFVewBBo/MxHkqlzoV8NBPuqsGVGw EcrK5gTrv5aEZDcALcEd+NvMYGbmgnt85l1VvZJY6wcYma2SUjTIf5+SbRaEEXL79v3kezdnlbq hGbDolS9j4WKnTn5SQg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-14_04,2026-09-14_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 impostorscore=0 spamscore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609140296 On Mon, 14 Sep 2026 11:35:07 +0530 "Aneesh Kumar K.V (Arm)" wrote: > The RSI SMCCC function IDs describe a firmware ABI and are not arm64 > architecture specific definitions. Follow-up changes need to use them from > non-arch code, including drivers/firmware/smccc and the Arm CCA guest > driver. > > Move the complete Realm Service Interface (RSI) implementation from > arch/arm64 to drivers/firmware/arm_rmm. The RSI SMCCC definitions and > command helpers are also moved to include/linux so they can be shared by > architecture code and firmware or driver code. This also keeps the > firmware interface outside architecture code, as requested [1]. > > [1] https://lore.kernel.org/all/agsNO9cc7H-b0H8L@willie-the-truck > > Reviewed-by: Jason Gunthorpe > Acked-by: Suzuki K Poulose > Signed-off-by: Aneesh Kumar K.V (Arm) Moving the code makes sense and indeed that is what the patch does so Reviewed-by: Jonathan Cameron Trivial gripe about the original code inline. > diff --git a/arch/arm64/include/asm/rsi_cmds.h b/include/linux/arm-rsi-cmds.h > similarity index 69% > rename from arch/arm64/include/asm/rsi_cmds.h > rename to include/linux/arm-rsi-cmds.h > index c1fab41f671e..9e8a8c189ca1 100644 > --- a/arch/arm64/include/asm/rsi_cmds.h > +++ b/include/linux/arm-rsi-cmds.h > > +static inline int rsi_set_memory_range(phys_addr_t start, phys_addr_t end, > + enum ripas state, unsigned long flags) > +{ > + unsigned long ret; > + phys_addr_t top; > + > + while (start != end) { > + ret = rsi_set_addr_range_state(start, end, state, flags, &top); > + if (ret || top < start || top > end) Obviously this is just code movement, but why eat the error value that rsi_set_addr_range_state() returns? > + return -EINVAL; > + start = top; > + } > + > + return 0; > +}