From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A07AA7A for ; Tue, 28 Jun 2022 19:04:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1656443084; x=1687979084; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=N1AIQgmubreattzHLRnM0HT3Yc8fAoLHRwgDBlBS8LA=; b=VHS+RJwDI+KcZ9uXXLcKfjF8faaFRG/l0XQvsCaWXKwlW1x5ZaY0iH2v NNh6KGSIr+W7CVP6Fmnx13j4jcHiqkpkv5M6brC2VSNCLYt8CTibCi0x4 CiYiFyJrEhIKy/mhdnt097oeht0B1aMYnewAp7p/fMR59QwOml/YmZdsq VkXAJQR/UrO9KlFEr+qJe7rsreBLBt3iuZltfYq2+xm3rNer4rbsFJ4gZ QV5jJfaO3Op8d2+jCpIJxf7tK+RHyneutpVp0TU77jnC3bA22YDAJnNsj sihrkprmfclvi8V00y20UQ9eaoW9NlGegolkPFJ9miuncpmKIj5UEHSt1 A==; X-IronPort-AV: E=McAfee;i="6400,9594,10392"; a="264865522" X-IronPort-AV: E=Sophos;i="5.92,229,1650956400"; d="scan'208";a="264865522" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jun 2022 12:04:44 -0700 X-IronPort-AV: E=Sophos;i="5.92,229,1650956400"; d="scan'208";a="587977804" Received: from staibmic-mobl1.amr.corp.intel.com (HELO [10.209.67.166]) ([10.209.67.166]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jun 2022 12:04:43 -0700 Message-ID: <33e38ba3-0865-8a9f-0739-af25a63d0beb@intel.com> Date: Tue, 28 Jun 2022 12:03:38 -0700 Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: [PATCH Part2 v6 06/49] x86/sev: Add helper functions for RMPUPDATE and PSMASH instruction Content-Language: en-US To: "Kalra, Ashish" , "Dr. David Alan Gilbert" Cc: "x86@kernel.org" , "linux-kernel@vger.kernel.org" , "kvm@vger.kernel.org" , "linux-coco@lists.linux.dev" , "linux-mm@kvack.org" , "linux-crypto@vger.kernel.org" , "tglx@linutronix.de" , "mingo@redhat.com" , "jroedel@suse.de" , "Lendacky, Thomas" , "hpa@zytor.com" , "ardb@kernel.org" , "pbonzini@redhat.com" , "seanjc@google.com" , "vkuznets@redhat.com" , "jmattson@google.com" , "luto@kernel.org" , "dave.hansen@linux.intel.com" , "slp@redhat.com" , "pgonda@google.com" , "peterz@infradead.org" , "srinivas.pandruvada@linux.intel.com" , "rientjes@google.com" , "dovmurik@linux.ibm.com" , "tobin@ibm.com" , "bp@alien8.de" , "Roth, Michael" , "vbabka@suse.cz" , "kirill@shutemov.name" , "ak@linux.intel.com" , "tony.luck@intel.com" , "marcorr@google.com" , "sathyanarayanan.kuppuswamy@linux.intel.com" , "alpergun@google.com" , "jarkko@kernel.org" References: From: Dave Hansen In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 6/28/22 10:57, Kalra, Ashish wrote: > + /* > + * RMP table entry format is not architectural and it can vary by processor and > + * is defined by the per-processor PPR. Restrict SNP support on the known CPU > + * model and family for which the RMP table entry format is currently defined for. > + */ > + if (family != 0x19 || model > 0xaf) > + goto nosnp; > + > > This way SNP will only be enabled specifically on the platforms for which this RMP entry > format is defined in those processor's PPR. This will work for Milan and Genoa as of now. At some point, it would be really nice if the AMD side of things could work to kick the magic number habit on these things. This: arch/x86/include/asm/intel-family.h has been really handy. It lets you do things like grep INTEL_FAM6_SKYLAKE arch/x86 That's a *LOT* more precise than: egrep -i '0x5E|94' arch/x86