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Sun, 02 Feb 2025 15:15:22 -0800 (PST) X-Google-Smtp-Source: AGHT+IE2mf76DirOg9TZyfOkrJfXsutpQ6g81h2feZA7/LYyJlI04cSOqf6NavNatW10Gphrl5eu/w== X-Received: by 2002:a17:903:120a:b0:216:3f6e:fabd with SMTP id d9443c01a7336-21edd7eafccmr173598665ad.7.1738538121968; Sun, 02 Feb 2025 15:15:21 -0800 (PST) Received: from [192.168.68.55] ([180.233.125.64]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21de32ea5fesm62974185ad.132.2025.02.02.15.15.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 02 Feb 2025 15:15:21 -0800 (PST) Message-ID: <34990c4f-b65e-4af2-8348-87ea078afc16@redhat.com> Date: Mon, 3 Feb 2025 09:15:12 +1000 Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 34/43] arm64: RME: Propagate number of breakpoints and watchpoints to userspace To: Steven Price , kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Jean-Philippe Brucker , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" References: <20241212155610.76522-1-steven.price@arm.com> <20241212155610.76522-35-steven.price@arm.com> From: Gavin Shan In-Reply-To: <20241212155610.76522-35-steven.price@arm.com> X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: zyueNCUASkE9JQPNh2fVNXRpPfL0iSqZWr6TXtgLDXQ_1738538122 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 12/13/24 1:55 AM, Steven Price wrote: > From: Jean-Philippe Brucker > > The RMM describes the maximum number of BPs/WPs available to the guest > in the Feature Register 0. Propagate those numbers into ID_AA64DFR0_EL1, > which is visible to userspace. A VMM needs this information in order to > set up realm parameters. > > Signed-off-by: Jean-Philippe Brucker > Signed-off-by: Steven Price > --- > arch/arm64/include/asm/kvm_rme.h | 2 ++ > arch/arm64/kvm/rme.c | 22 ++++++++++++++++++++++ > arch/arm64/kvm/sys_regs.c | 2 +- > 3 files changed, 25 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/kvm_rme.h b/arch/arm64/include/asm/kvm_rme.h > index 0d89ab1645c1..f8e37907e2d5 100644 > --- a/arch/arm64/include/asm/kvm_rme.h > +++ b/arch/arm64/include/asm/kvm_rme.h > @@ -85,6 +85,8 @@ void kvm_init_rme(void); > u32 kvm_realm_ipa_limit(void); > u32 kvm_realm_vgic_nr_lr(void); > > +u64 kvm_realm_reset_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val); > + > bool kvm_rme_supports_sve(void); > > int kvm_realm_enable_cap(struct kvm *kvm, struct kvm_enable_cap *cap); > diff --git a/arch/arm64/kvm/rme.c b/arch/arm64/kvm/rme.c > index e562e77c1f94..d21042d5ec9a 100644 > --- a/arch/arm64/kvm/rme.c > +++ b/arch/arm64/kvm/rme.c > @@ -63,6 +63,28 @@ u32 kvm_realm_vgic_nr_lr(void) > return u64_get_bits(rmm_feat_reg0, RMI_FEATURE_REGISTER_0_GICV3_NUM_LRS); > } > > +u64 kvm_realm_reset_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val) > +{ > + u32 bps = u64_get_bits(rmm_feat_reg0, RMI_FEATURE_REGISTER_0_NUM_BPS); > + u32 wps = u64_get_bits(rmm_feat_reg0, RMI_FEATURE_REGISTER_0_NUM_WPS); > + u32 ctx_cmps; > + > + if (!kvm_is_realm(vcpu->kvm)) > + return val; > + > + /* Ensure CTX_CMPs is still valid */ > + ctx_cmps = FIELD_GET(ID_AA64DFR0_EL1_CTX_CMPs, val); > + ctx_cmps = min(bps, ctx_cmps); > + > + val &= ~(ID_AA64DFR0_EL1_BRPs_MASK | ID_AA64DFR0_EL1_WRPs_MASK | > + ID_AA64DFR0_EL1_CTX_CMPs); > + val |= FIELD_PREP(ID_AA64DFR0_EL1_BRPs_MASK, bps) | > + FIELD_PREP(ID_AA64DFR0_EL1_WRPs_MASK, wps) | > + FIELD_PREP(ID_AA64DFR0_EL1_CTX_CMPs, ctx_cmps); > + > + return val; > +} > + The the filed ID_AA64DFR0_EL1_WRPs_MASK of the system register ID_AA64DFR0_EL1 is writtable, as declared in sys_reg.c. We need to consolidate the field when the system register is written. ID_FILTERED(ID_AA64DFR0_EL1, id_aa64dfr0_el1, ID_AA64DFR0_EL1_DoubleLock_MASK | ID_AA64DFR0_EL1_WRPs_MASK | ID_AA64DFR0_EL1_PMUVer_MASK | ID_AA64DFR0_EL1_DebugVer_MASK), > static int get_start_level(struct realm *realm) > { > return 4 - stage2_pgtable_levels(realm->ia_bits); > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index a4713609e230..55cde43b36b9 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -1806,7 +1806,7 @@ static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val) > /* Hide SPE from guests */ > val &= ~ID_AA64DFR0_EL1_PMSVer_MASK; > > - return val; > + return kvm_realm_reset_id_aa64dfr0_el1(vcpu, val); > } > > static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, Thanks, Gavin