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From: Dave Hansen <dave.hansen@intel.com>
To: isaku.yamahata@intel.com, kvm@vger.kernel.org,
	linux-kernel@vger.kernel.org
Cc: isaku.yamahata@gmail.com, Michael Roth <michael.roth@amd.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Sean Christopherson <seanjc@google.com>,
	linux-coco@lists.linux.dev,
	Chao Peng <chao.p.peng@linux.intel.com>,
	Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>,
	Borislav Petkov <bp@suse.de>
Subject: Re: [PATCH 01/12] x86/mce: Fix hw MCE injection feature detection
Date: Fri, 13 Oct 2023 08:05:54 -0700	[thread overview]
Message-ID: <532fd5c3-dddb-4503-9b81-31c3d07a7119@intel.com> (raw)
In-Reply-To: <23c6fa20777498bccd486aedc435eef9af174748.1696926843.git.isaku.yamahata@intel.com>

[-- Attachment #1: Type: text/plain, Size: 2116 bytes --]

Isaku, when you report a bug, it would be great to include the folks who
authored and worked on the original patch that introduced the bug.  I've
gone ahead and done that for you here.

On 10/10/23 01:35, isaku.yamahata@intel.com wrote:
> From: Isaku Yamahata <isaku.yamahata@intel.com>
> 
> When initializing x86 MCE injection framework, it checks if hardware mce
> injection is available or not.  When it's not available on AMD, set the
> boolean variable to false to not use it.  The variable is on by default and
> the feature is AMD specific based on the code.
> 
> Because the variable is default on, it is true on Intel platform (probably
> on other non-AMD x86 platform).  It results in unchecked msr access of
> MSR_K7_HWCR=0xc0010015 when injecting MCE on Intel platform.  (Probably on
> other x86 platform.)
> 
> Make the variable of by default, and set the variable on when the hardware
> feature is usable.

Gah, I'm finding that changelog impenetrable.  Here's what's missing:

  * The entirety of check_hw_inj_possible() is for AMD hardware:
    X86_FEATURE_SMCA, the MSRs, hw_injection_possible, everything.
  * Only AMD systems with SMCA support hardware error injection
    (anything other than "echo sw > /sys/kernel/debug/mce-inject/flags")
  * That AMD-only restriction is enforced by 'hw_injection_possible'
  * 'hw_injection_possible' is true by default and only set to false in
    check_hw_inj_possible() ... the AMD-only code

The end result is that everyone except SMCA-enabled AMD systems (Intel
included) leaves hw_injection_possible=true.  They are free to try and
inject hardware errors.  If they do, they'll get errors when writing to
the MSRs.

To fix this, make disable hw_injection_possible by default.  Only enable
it on SMCA hardware that actually succeeds in ... whatever:

                wrmsrl_safe(mca_msr_reg(bank, MCA_STATUS), status);
                rdmsrl_safe(mca_msr_reg(bank, MCA_STATUS), &status);

is doing.

... and don't do it at the top of the function.  Why bother setting it
to true only to disable it a moment later?

Do something like the following instead.

[-- Attachment #2: amdmce.patch --]
[-- Type: text/x-patch, Size: 734 bytes --]

diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inject.c
index 4d8d4bcf915d..01ee886d8540 100644
--- a/arch/x86/kernel/cpu/mce/inject.c
+++ b/arch/x86/kernel/cpu/mce/inject.c
@@ -33,7 +33,7 @@
 
 #include "internal.h"
 
-static bool hw_injection_possible = true;
+static bool hw_injection_possible;
 
 /*
  * Collect all the MCi_XXX settings
@@ -748,9 +748,10 @@ static void check_hw_inj_possible(void)
 		rdmsrl_safe(mca_msr_reg(bank, MCA_STATUS), &status);
 
 		if (!status) {
-			hw_injection_possible = false;
 			pr_warn("Platform does not allow *hardware* error injection."
 				"Try using APEI EINJ instead.\n");
+		} else {
+			hw_injection_possible = true;
 		}
 
 		toggle_hw_mce_inject(cpu, false);

  reply	other threads:[~2023-10-13 15:07 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-10  8:35 [PATCH 00/12] x86/mce, KVM: X86: KVM memory poison and MCE injector support isaku.yamahata
2023-10-10  8:35 ` [PATCH 01/12] x86/mce: Fix hw MCE injection feature detection isaku.yamahata
2023-10-13 15:05   ` Dave Hansen [this message]
2023-10-10  8:35 ` [PATCH 02/12] X86/mce/inject: Add mcgstatus for mce-inject debugfs isaku.yamahata
2023-10-10  8:35 ` [PATCH 03/12] x86/mce/inject: Add notrigger entry to suppress MCE injection isaku.yamahata
2023-10-10  8:35 ` [PATCH 04/12] x86/mce: Move and export inject_mce() from inject.c to core.c isaku.yamahata
2023-10-10  8:35 ` [PATCH 05/12] mm/fadvise: Add flags to inject hwpoison for posix_fadvise() isaku.yamahata
2023-10-10  8:35 ` [PATCH 06/12] mm/fadvise: Add FADV_MCE_INJECT flag " isaku.yamahata
2023-10-10  8:35 ` [PATCH 07/12] x86/mce/inject: Wire up the x86 MCE injector to FADV_MCE_INJECT isaku.yamahata
2023-10-10  8:35 ` [PATCH 08/12] x86/mce: Define a notifier chain for mce injector isaku.yamahata
2023-10-10  8:35 ` [PATCH 09/12] KVM: X86: Add debugfs to inject machine check on VM exit isaku.yamahata
2023-10-20  0:38   ` Sean Christopherson
2023-10-10  8:35 ` [PATCH 10/12] KVM: selftests: Allow mapping guest memory without host alias isaku.yamahata
2023-10-10  8:35 ` [PATCH 11/12] KVM: selftests: lib: Add src memory type for hwpoison test isaku.yamahata
2023-10-10  8:35 ` [PATCH 12/12] KVM: selftests: hwpoison/mce failure injection isaku.yamahata

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