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X-CSE-ConnectionGUID: A5O02aaAS+2IS2r7crSyZQ== X-CSE-MsgGUID: rjZngqQeRyCHtvau4n3bkA== X-IronPort-AV: E=McAfee;i="6800,10657,11686"; a="58619295" X-IronPort-AV: E=Sophos;i="6.21,263,1763452800"; d="scan'208";a="58619295" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2026 08:02:17 -0800 X-CSE-ConnectionGUID: 9QbDEhyDTVaanvwau77IEQ== X-CSE-MsgGUID: VTnVV3Y+T8eXE+VTy3ITlg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,263,1763452800"; d="scan'208";a="208993848" Received: from cjhill-mobl.amr.corp.intel.com (HELO [10.125.110.58]) ([10.125.110.58]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2026 08:02:16 -0800 Message-ID: <56a62e54-59f7-4423-9f01-4472d5c3815d@intel.com> Date: Fri, 30 Jan 2026 08:02:15 -0800 Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 09/26] coco/tdx-host: Expose P-SEAMLDR information via sysfs To: Chao Gao Cc: linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, x86@kernel.org, reinette.chatre@intel.com, ira.weiny@intel.com, kai.huang@intel.com, dan.j.williams@intel.com, yilun.xu@linux.intel.com, sagis@google.com, vannapurve@google.com, paulmck@kernel.org, nik.borisov@suse.com, zhenzhong.duan@intel.com, seanjc@google.com, rick.p.edgecombe@intel.com, kas@kernel.org, dave.hansen@linux.intel.com, vishal.l.verma@intel.com, Farrah Chen References: <20260123145645.90444-1-chao.gao@intel.com> <20260123145645.90444-10-chao.gao@intel.com> <9fb1bbf3-0623-447e-86d7-d48ef20fb42c@intel.com> From: Dave Hansen Content-Language: en-US Autocrypt: addr=dave.hansen@intel.com; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 1/30/26 06:44, Chao Gao wrote: >>> +What: /sys/devices/faux/tdx_host/seamldr/num_remaining_updates >>> +Contact: linux-coco@lists.linux.dev >>> +Description: (RO) Report the number of remaining updates that can be performed. >>> + The CPU keeps track of TCB versions for each TDX Module that >>> + has been loaded. Since this tracking database has finite >>> + capacity, there's a maximum number of Module updates that can >>> + be performed. >> >> Is it really the CPU? Or some SEAM software construct? > > It is the CPU. The CPU provides the database and gives instructions to > P-SEAMLDR for adding records or cleaning up the entire database. Either way, it's an implementation detail that doesn't need to be litigated in the OS ABI docs. TDX maintains a log about each TDX module which has been loaded. This log has a finite size which limits the number of TDX module updates which can be performed. Report the number of updates remaining. >>> +#ifdef CONFIG_INTEL_TDX_MODULE_UPDATE ... > /facepalm. Sorry for missing these important considerations. > > I overlooked a critical constraint: only one CPU can call P-SEAMLDR at a time; > any second CPU gets VMFailInvalid. Patch 19 adds a lock for SEAMLDR.INSTALL > serialization, but we actually need to serialize all P-SEAMLDR calls or handle > VMFailInvalid with retries. > > I will make the following changes to see how they look: > > 1. Move the lock from patch 19 to seamldr_call() to serialize all P-SEAMLDR calls Ack, yes, this is obviously required. > 2. Cache seamldr_info and only update it after successful updates > 3. Make seamldr_get_info() return cached data instead of calling P-SEAMLDR every time To be honest, I'm not sure we need a cache. Why don't we just make the permissions 400 and keep the info structure on the stack?