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[175.34.62.5]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-77f30749642sm2123356b3a.100.2025.09.21.17.03.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 21 Sep 2025 17:03:41 -0700 (PDT) Message-ID: <59d78787-1871-41ba-9a2e-30d1596c021f@redhat.com> Date: Mon, 22 Sep 2025 10:03:32 +1000 Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v10 32/43] arm64: RME: Enable PMU support with a realm guest To: Steven Price , kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve References: <20250820145606.180644-1-steven.price@arm.com> <20250820145606.180644-33-steven.price@arm.com> From: Gavin Shan In-Reply-To: <20250820145606.180644-33-steven.price@arm.com> X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: sCDXHbut23Bx74kDDiz4s8KMzCpwyKpLUDmoYvP2MoQ_1758499422 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 8/21/25 12:55 AM, Steven Price wrote: > Use the PMU registers from the RmiRecExit structure to identify when an > overflow interrupt is due and inject it into the guest. Also hook up the > configuration option for enabling the PMU within the guest. > > When entering a realm guest with a PMU interrupt pending, it is > necessary to disable the physical interrupt. Otherwise when the RMM > restores the PMU state the physical interrupt will trigger causing an > immediate exit back to the host. The guest is expected to acknowledge > the interrupt causing a host exit (to update the GIC state) which gives > the opportunity to re-enable the physical interrupt before the next PMU > event. > > Number of PMU counters is configured by the VMM by writing to PMCR.N. > > Signed-off-by: Steven Price > --- > Changes since v2: > * Add a macro kvm_pmu_get_irq_level() to avoid compile issues when PMU > support is disabled. > --- > arch/arm64/kvm/arm.c | 11 +++++++++++ > arch/arm64/kvm/guest.c | 7 +++++++ > arch/arm64/kvm/pmu-emul.c | 3 +++ > arch/arm64/kvm/rme.c | 8 ++++++++ > arch/arm64/kvm/sys_regs.c | 5 +++-- > include/kvm/arm_pmu.h | 4 ++++ > 6 files changed, 36 insertions(+), 2 deletions(-) > Reviewed-by: Gavin Shan