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From: Dan Williams <dan.j.williams@intel.com>
To: Alexey Kardashevskiy <aik@amd.com>,
	Dan Williams <dan.j.williams@intel.com>,
	<linux-coco@lists.linux.dev>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
	Lukas Wunner <lukas@wunner.de>, Samuel Ortiz <sameo@rivosinc.com>,
	Xu Yilun <yilun.xu@linux.intel.com>, <linux-pci@vger.kernel.org>,
	<gregkh@linuxfoundation.org>
Subject: Re: [PATCH 08/11] PCI/IDE: Add IDE establishment helpers
Date: Thu, 20 Feb 2025 13:44:21 -0800	[thread overview]
Message-ID: <67b7a2351d003_2d2c29496@dwillia2-xfh.jf.intel.com.notmuch> (raw)
In-Reply-To: <ad512345-793b-4cfe-a71b-445f2be64df5@amd.com>

Alexey Kardashevskiy wrote:
> On 6/12/24 09:24, Dan Williams wrote:
> > There are two components to establishing an encrypted link, provisioning
> > the stream in config-space, and programming the keys into the link layer
> > via the IDE_KM (key management) protocol. These helpers enable the
> > former, and are in support of TSM coordinated IDE_KM. When / if native
> > IDE establishment arrives it will share this same config-space
> > provisioning flow, but for now IDE_KM, in any form, is saved for a
> > follow-on change.
> > 
> > With the TSM implementations of SEV-TIO and TDX Connect in mind this
> > abstracts small differences in those implementations. For example, TDX
> > Connect handles Root Port registers updates while SEV-TIO expects System
> > Software to update the Root Port registers. This is the rationale for
> > the PCI_IDE_SETUP_ROOT_PORT flag.
> > 
> > The other design detail for TSM-coordinated IDE establishment is that
> > the TSM manages allocation of stream-ids, this is why the stream_id is
> > passed in to pci_ide_stream_setup().
> > 
> > The flow is:
> > 
> > pci_ide_stream_probe()
> >    Gather stream settings (devid and address filters)
> > pci_ide_stream_setup()
> >    Program the stream settings into the endpoint, and optionally Root Port)
> > pci_ide_enable_stream()
> >    Run the stream after IDE_KM
> > 
> > In support of system administrators auditing where platform IDE stream
> > resources are being spent, the allocated stream is reflected as a
> > symlink from the host-bridge to the endpoint.
> > 
> > Thanks to Wu Hao for a draft implementation of this infrastructure.
> > 
> > Cc: Bjorn Helgaas <bhelgaas@google.com>
> > Cc: Lukas Wunner <lukas@wunner.de>
> > Cc: Samuel Ortiz <sameo@rivosinc.com>
> > Co-developed-by: Alexey Kardashevskiy <aik@amd.com>
> > Signed-off-by: Alexey Kardashevskiy <aik@amd.com>
> > Co-developed-by: Xu Yilun <yilun.xu@linux.intel.com>
> > Signed-off-by: Xu Yilun <yilun.xu@linux.intel.com>
> > Signed-off-by: Dan Williams <dan.j.williams@intel.com>
[..]
> > @@ -71,3 +74,192 @@ void pci_ide_init(struct pci_dev *pdev)
> >   	pdev->sel_ide_cap = sel_ide_cap;
> >   	pdev->nr_ide_mem = nr_ide_mem;
> >   }
> > +
> > +void pci_init_host_bridge_ide(struct pci_host_bridge *hb)
> > +{
> > +	hb->ide_stream_res =
> > +		DEFINE_RES_MEM_NAMED(0, 0, "IDE Address Association");
> 
> out of curiosity - should it be DEFINE_RES_MEM_NAMED(0, UINT_MAX, "IDE 
> Address Association");?

Hmm, yes, an empty resource only makes sense if there is going to be a
later point in the init flow where it is adjusted to map the real
platform probed boundaries, and I do not have that in this code.

The platform iomem_resource boundaries should be settled before the
host-bridge is initialized, so no need to find a later point than this
to set the bounds. Will fold in this incremental change:

@@ -77,8 +77,13 @@ void pci_ide_init(struct pci_dev *pdev)
 
 void pci_init_host_bridge_ide(struct pci_host_bridge *hb)
 {
-       hb->ide_stream_res =
-               DEFINE_RES_MEM_NAMED(0, 0, "IDE Address Association");
+       /*
+        * Match platform iomem resource boundaries for IDE address
+        * association.
+        */
+       hb->ide_stream_res = DEFINE_RES_MEM_NAMED(
+               iomem_resource.start, resource_size(&iomem_resource),
+               "IDE Address Association");
 }
 
 /*


[..]
> > +void pci_ide_enable_stream(struct pci_dev *pdev, struct pci_ide *ide)
> > +{
> > +	int pos;
> > +	u32 val;
> > +
> > +	pos = sel_ide_offset(pdev->sel_ide_cap, ide->stream_id,
> > +			     pdev->nr_ide_mem);
> > +
> > +	val = FIELD_PREP(PCI_IDE_SEL_CTL_ID_MASK, ide->stream_id) |
> > +	      FIELD_PREP(PCI_IDE_SEL_CTL_DEFAULT, 1);
> 
> 
> FIELD_PREP(PCI_IDE_SEL_CTL_EN) is missing here.

Added.

> And no PCI_IDE_SETUP_ROOT_PORT here, is the platform expected to enable 
> it explicitely? If yes, then we do not need PCI_IDE_SETUP_ROOT_PORT 
> really. If no, then this needs to enable the stream on the rootport.

Hmm, yes, looking at this now, PCI_IDE_SETUP_ROOT_PORT is giving off
"mid-layer" smells and this responsibility should be pushed to the low
level driver.

It is still the case that there is a part of the stream setup that can
fail, like registering the presence of the stream in sysfs, but the
piece that can not fail, __pci_ide_stream_setup(), should be left to the
platform TSM driver to optionally be called for the root-port.

I will rename the parts of the stream setup that needs alloc / free as
"pci_ide_stream_{register,unregister}()", export
__pci_ide_stream_setup() as a standalone helper renamed to just
pci_ide_stream_setup(), and drop the PCI_IDE_SETUP_ROOT_PORT flag
concept.

> Also, my test device wants PCI_IDE_SEL_CTL_TEE_LIMITED to work, I wonder 
> how to showel it in here, add a "unsigned dev_sel_ctl" to pci_ide?
> And the same comment for PCI_IDE_SEL_CTL_CFG_EN on the rootport. 
> "unsigned rootport_sel_ctl"?

I will add that. If the device supports limited stream I see no reason
that Linux would want to not require it (outside of device quirks). So,
the default will be to enable it if supported, but the low-level TSM
driver can always clear that support flag in the pdev (endpoint or root)
if the need arises.

[..]
> > diff --git a/include/linux/pci-ide.h b/include/linux/pci-ide.h
> > new file mode 100644
> > index 000000000000..24e08a413645
> > --- /dev/null
> > +++ b/include/linux/pci-ide.h
> > @@ -0,0 +1,33 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/* Copyright(c) 2024 Intel Corporation. All rights reserved. */
> > +
> > +/* PCIe 6.2 section 6.33 Integrity & Data Encryption (IDE) */
> > +
> > +#ifndef __PCI_IDE_H__
> > +#define __PCI_IDE_H__
> > +
> > +#include <linux/range.h>
> > +
> > +struct pci_ide {
> > +	int domain;
> 
> Not much point in caching this, real easy to calculate in that one spot.

Agree, added an ide_domain_nr() helper to meet the requirement that
software must write 0 if the device has not captured its segment base.

> Thanks,
> 
> ps. I'll probably be commenting more on the same things as I try using 
> all this :)

Hey, yes please! The whole point of this effort is to find a path to
mutual acceptance on all these concerns.

  reply	other threads:[~2025-02-20 21:44 UTC|newest]

Thread overview: 125+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-12-05 22:23 [PATCH 00/11] PCI/TSM: Core infrastructure for PCI device security (TDISP) Dan Williams
2024-12-05 22:23 ` [PATCH 01/11] configfs-tsm: Namespace TSM report symbols Dan Williams
2024-12-10  6:08   ` Alexey Kardashevskiy
2024-12-11 13:55   ` Suzuki K Poulose
2024-12-05 22:23 ` [PATCH 02/11] coco/guest: Move shared guest CC infrastructure to drivers/virt/coco/guest/ Dan Williams
2024-12-10  6:09   ` Alexey Kardashevskiy
2024-12-05 22:23 ` [PATCH 03/11] coco/tsm: Introduce a class device for TEE Security Managers Dan Williams
2025-01-28 12:17   ` Jonathan Cameron
2025-02-25 21:08     ` Dan Williams
2024-12-05 22:23 ` [PATCH 04/11] PCI/IDE: Selective Stream IDE enumeration Dan Williams
2024-12-10  3:08   ` Aneesh Kumar K.V
2024-12-12  6:32     ` Xu Yilun
2025-02-22  0:42       ` Dan Williams
2025-02-20  3:17     ` Dan Williams
2024-12-10  6:18   ` Alexey Kardashevskiy
2025-02-20  3:59     ` Dan Williams
2024-12-10  7:05   ` Alexey Kardashevskiy
2024-12-12  6:06     ` Xu Yilun
2024-12-18 10:35       ` Alexey Kardashevskiy
2025-02-22  0:30       ` Dan Williams
2025-02-20 18:07     ` Dan Williams
2025-02-21  0:53       ` Alexey Kardashevskiy
2025-02-27 23:46         ` Dan Williams
2024-12-10 19:24   ` Bjorn Helgaas
2025-02-22  0:13     ` Dan Williams
2025-01-30 10:45   ` Jonathan Cameron
2025-02-26  0:21     ` Dan Williams
2024-12-05 22:23 ` [PATCH 05/11] PCI/TSM: Authenticate devices via platform TSM Dan Williams
2024-12-10 10:18   ` Alexey Kardashevskiy
2025-02-21  8:13     ` Aneesh Kumar K.V
2025-02-25  7:17       ` Xu Yilun
2025-02-26 12:10         ` Aneesh Kumar K.V
2025-02-26 12:13           ` [RFC PATCH 1/7] tsm: Select PCI_DOE which is required for PCI_TSM Aneesh Kumar K.V (Arm)
2025-02-26 12:13             ` [RFC PATCH 2/7] tsm: Move tsm core outside the host directory Aneesh Kumar K.V (Arm)
2025-02-26 12:13             ` [RFC PATCH 3/7] tsm: vfio: Add tsm bind/unbind support Aneesh Kumar K.V (Arm)
2025-02-26 12:13             ` [RFC PATCH 4/7] tsm: Allow tsm ops function to be called for multi-function devices Aneesh Kumar K.V (Arm)
2025-02-26 12:13             ` [RFC PATCH 5/7] tsm: Don't error out for doe mailbox failure Aneesh Kumar K.V (Arm)
2025-02-26 12:13             ` [RFC PATCH 6/7] tsm: Allow tsm connect ops to be used for multiple operations Aneesh Kumar K.V (Arm)
2025-02-26 12:13             ` [RFC PATCH 7/7] tsm: Add secure SPDM support Aneesh Kumar K.V (Arm)
2025-02-27  6:50               ` Xu Yilun
2025-02-27  6:35           ` [PATCH 05/11] PCI/TSM: Authenticate devices via platform TSM Xu Yilun
2025-02-27 13:57             ` Aneesh Kumar K.V
2025-02-28  1:26               ` Xu Yilun
2025-02-28  9:48                 ` Aneesh Kumar K.V
2025-03-01  7:50                   ` Xu Yilun
2025-03-07  3:07                   ` Alexey Kardashevskiy
2025-02-27 19:53           ` Dan Williams
2025-02-28 10:06             ` Aneesh Kumar K.V
2025-02-21 20:42     ` Dan Williams
2025-02-25  4:45       ` Alexey Kardashevskiy
2025-02-28  3:09         ` Dan Williams
2024-12-10 18:52   ` Bjorn Helgaas
2025-02-21 22:32     ` Dan Williams
2024-12-12  9:50   ` Xu Yilun
2025-02-22  1:15     ` Dan Williams
2025-02-24 11:02       ` Xu Yilun
2025-02-28  0:15         ` Dan Williams
2025-02-28  9:39           ` Xu Yilun
2025-01-30 11:45   ` Jonathan Cameron
2025-02-26  0:50     ` Dan Williams
2024-12-05 22:23 ` [PATCH 06/11] samples/devsec: PCI device-security bus / endpoint sample Dan Williams
2024-12-06  4:23   ` kernel test robot
2024-12-09  3:40   ` kernel test robot
2025-01-30 13:21   ` Jonathan Cameron
2025-02-26  2:00     ` Dan Williams
2024-12-05 22:23 ` [PATCH 07/11] PCI: Add PCIe Device 3 Extended Capability enumeration Dan Williams
2024-12-09 13:17   ` Ilpo Järvinen
2025-02-20  3:05     ` Dan Williams
2025-02-20  3:09       ` Dan Williams
2024-12-10 19:21   ` Bjorn Helgaas
2024-12-11 13:22     ` Ilpo Järvinen
2025-02-22  0:15       ` Dan Williams
2025-02-24 15:09         ` Ilpo Järvinen
2025-02-28  0:29           ` Dan Williams
2025-02-21 23:34     ` Dan Williams
2025-02-25  2:25       ` Alexey Kardashevskiy
2024-12-05 22:24 ` [PATCH 08/11] PCI/IDE: Add IDE establishment helpers Dan Williams
2024-12-10  3:19   ` Aneesh Kumar K.V
2024-12-10  3:37     ` Aneesh Kumar K.V
2025-02-20  3:39       ` Dan Williams
2025-02-21 15:53         ` Aneesh Kumar K.V
2025-02-25  0:46           ` Dan Williams
2025-01-07 20:19     ` Xu Yilun
2025-01-10 13:25       ` Aneesh Kumar K.V
2025-02-24 22:31         ` Dan Williams
2025-02-25  2:29           ` Alexey Kardashevskiy
2025-02-20  3:28     ` Dan Williams
2024-12-10  7:07   ` Alexey Kardashevskiy
2025-02-20 21:44     ` Dan Williams [this message]
2024-12-10 18:47   ` Bjorn Helgaas
2025-02-21 22:02     ` Dan Williams
2024-12-12 10:50   ` Xu Yilun
2024-12-19  7:25   ` Alexey Kardashevskiy
2024-12-19 10:05     ` Alexey Kardashevskiy
2025-01-07 20:00       ` Xu Yilun
2025-01-09  2:35         ` Alexey Kardashevskiy
2025-01-09 21:28           ` Xu Yilun
2025-01-15  0:20             ` Alexey Kardashevskiy
2025-02-25  0:06               ` Dan Williams
2025-02-25  3:39                 ` Alexey Kardashevskiy
2025-02-28  2:26                   ` Dan Williams
2025-03-04  0:03                     ` Alexey Kardashevskiy
2025-03-04  0:57                       ` Dan Williams
2025-03-04  1:31                         ` Alexey Kardashevskiy
2025-03-04 17:59                           ` Dan Williams
2025-02-20  4:19             ` Alexey Kardashevskiy
2025-02-24 22:24         ` Dan Williams
2025-02-25  2:45           ` Xu Yilun
2025-02-24 20:28       ` Dan Williams
2025-02-26  1:54         ` Alexey Kardashevskiy
2025-02-24 20:24     ` Dan Williams
2025-02-25  5:01       ` Xu Yilun
2024-12-05 22:24 ` [PATCH 09/11] PCI/IDE: Report available IDE streams Dan Williams
2024-12-06  0:12   ` kernel test robot
2024-12-06  0:43   ` kernel test robot
2025-02-11  6:10   ` Alexey Kardashevskiy
2025-02-27 23:35     ` Dan Williams
2024-12-05 22:24 ` [PATCH 10/11] PCI/TSM: Report active " Dan Williams
2024-12-10 18:49   ` Bjorn Helgaas
2025-02-21 22:28     ` Dan Williams
2024-12-05 22:24 ` [PATCH 11/11] samples/devsec: Add sample IDE establishment Dan Williams
2025-01-30 13:39   ` Jonathan Cameron
2025-02-27 23:27     ` Dan Williams
2024-12-06  6:05 ` [PATCH 00/11] PCI/TSM: Core infrastructure for PCI device security (TDISP) Greg KH
2024-12-06  8:44   ` Dan Williams

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