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Fri, 25 Apr 2025 23:31:31 +0000 Date: Fri, 25 Apr 2025 16:31:28 -0700 From: Dan Williams To: Aneesh Kumar K.V , Dan Williams , CC: Bjorn Helgaas , Lukas Wunner , Samuel Ortiz , Alexey Kardashevskiy , "Xu Yilun" , , Subject: Re: [PATCH v2 08/11] PCI/IDE: Add IDE establishment helpers Message-ID: <680c1b50443bf_1d5229484@dwillia2-xfh.jf.intel.com.notmuch> References: <174107245357.1288555.10863541957822891561.stgit@dwillia2-xfh.jf.intel.com> <174107250147.1288555.16948528371146013276.stgit@dwillia2-xfh.jf.intel.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-ClientProxiedBy: MW4PR04CA0387.namprd04.prod.outlook.com (2603:10b6:303:81::32) To PH8PR11MB8107.namprd11.prod.outlook.com (2603:10b6:510:256::6) Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH8PR11MB8107:EE_|SA1PR11MB6895:EE_ X-MS-Office365-Filtering-Correlation-Id: 76afb5dd-1dba-4828-b3c0-08dd84514f17 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|376014; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?izfd4cinuBXEF44s0MXcCP6l8pXLu6Bta4LfmHVtke7OvkNApQczhowpHl5e?= =?us-ascii?Q?hUhR9N9qdLrAogsEKNzD77WNiVAYSZHCDIn6xjo51Do8hFcT7220031KCusq?= =?us-ascii?Q?jJuFOLTscQrp0sTBoWD07gOUX/sklZlfRokz4O3De4KONyJGFR1Q5+tsQApa?= =?us-ascii?Q?tLsHCep+y9GFFfiVW3Uss0el7BNj3lx+hi8JhEBf81lQPPixHwoF+m23G0qY?= =?us-ascii?Q?FNfL7p19vhMTShhLQ76Cw9gf4IWnNBR/IVJW8uORo59/9+hBU7TCK/w/L0kX?= =?us-ascii?Q?7ZHg73kCT5N654mAwLPRzl92jdUORLjmHCdxBrl3NPRVdYldRAr7evtCRgmO?= =?us-ascii?Q?1GmXzTtgUup9aNHrZ/LYm5VcWmHrEAc4gb2RMJDV2BZg4/cwZ+hZBf5lglVW?= =?us-ascii?Q?rMYFbk6byLZTMmBuQ8PIA8jKj/w3eT/kvD//IVYyVzofYjd+FJ22zI8DndhB?= =?us-ascii?Q?pPL/ALsBVe13ksiY2SQ2V3hjrHpq1kl0IQmYudgjcVCW6bws3zYPucU1d6pS?= =?us-ascii?Q?61Er1Bx7s9q1jdmziCg185DhiE+TbbSGilrzG/TVWHyuGSvmSNTKpiv+lBk/?= =?us-ascii?Q?VT5xX0tMiBGID0aW20um9PO0SaufvLmh/2KvZV+O20S0Ix+1TzAP9ijIubPZ?= =?us-ascii?Q?1PGzVCgpwN7qJXG/mhzjTkhYyLcJg5pC0GSeAyVFyVCs5bB1D83g/+eSbWFb?= =?us-ascii?Q?rfxX5Cagg/WUGXaaD4W7e2r67B/Q6/kkyiljS+uk7qN30TAxg7lb8y4LT1bu?= =?us-ascii?Q?1l/ubDk9DGNajdcUiWsvpVUGyDUE04veRIgg5sm8X+GalXVs9Rd9VeBK+EZh?= =?us-ascii?Q?XhhcJrORMyQnCgtvgNSRU5b3+YQq0H+HY8+1vBf7IQATWrp6bLX3hiop1edf?= =?us-ascii?Q?9XS3RuAYi811qPTRtxjpOsRNo6snZ/zmftogl09SGjvdtzwHajeBX/+yWsPP?= =?us-ascii?Q?w1Vh3O2Lq3ZBEV4JBQwtowpRyxp76lBOcTlztJ6WnbbbGNQ3XnWDAsz2aI23?= =?us-ascii?Q?HmL7enVjpMtSaJSVlGcJ+zn0Dkz2qyjJ089UvNgcQiTDKirCtRcuJTJGiimK?= =?us-ascii?Q?0oSSPRGKhpYDfu7P87opQF0FwAyuwgrFfFRTtykSXvJ6qHR0wCH1bjuQu51Q?= =?us-ascii?Q?Yba+KBrqDwaS3JOUug6YYAFjv4wTGuKCAymzmDX+h5zr1a6pwxNNTWzmdhux?= =?us-ascii?Q?pEantP1xKAGqqADpOOVC6g7GBfE9zLqERRrzQ8A9UIAZHavocJVgTq2dm/wS?= =?us-ascii?Q?S3xdNmRcnljSM+zo14+ynfaEx1k5oy/NJl/pgfBxjEdiieTnE7v2N4Zu0YQ/?= =?us-ascii?Q?l8S/teCyoyz+g/MZpdRcXFe3BdhHTeRy448u8/Nfr1N0LFERnF396Jha4aBz?= =?us-ascii?Q?7yICNnEYZlHoIAQe8egiO0DqAA7dJuJg4nITnyU8SYiN3kPA+W3Ohn6VBlvD?= =?us-ascii?Q?GgAIWC6hp+TbUOfqALxTfEipCOm2oiKyraHctgDCEmZoh1Y+Yc3QNTEBG/0m?= =?us-ascii?Q?PXPT1DpngOxLffHK1o50RrI34I/iQfmdtkyZH4tHUu3PSOwlAZ8OBD7Y3ToR?= =?us-ascii?Q?tBe6Cz1FQSi2vSe1JwxNHBa/YeEH4Lfk1o35OaZB+4YpG62XwUvGDGTorip6?= =?us-ascii?Q?LQ=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: 76afb5dd-1dba-4828-b3c0-08dd84514f17 X-MS-Exchange-CrossTenant-AuthSource: PH8PR11MB8107.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Apr 2025 23:31:31.3222 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Tei17I+fmpCRhzGwcgVFBIvbp1htTtsaLn/8voYnOePGKcCHYJZEKNCLmNKfbv0ISe4vPqQRFn3EmTv6xsse6mxJFh+0JKp50V64AWzq6f8= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR11MB6895 X-OriginatorOrg: intel.com Aneesh Kumar K.V wrote: > Dan Williams writes: > > > There are two components to establishing an encrypted link, provisioning > > the stream in Partner Port config-space, and programming the keys into > > the link layer via IDE_KM (IDE Key Management). This new library, > > drivers/pci/ide.c, enables the former. IDE_KM, via a TSM low-level > > driver, is saved for later. > > > .... > > > +/** > > + * pci_ide_stream_setup() - program settings to Selective IDE Stream registers > > + * @pdev: PCIe device object for either a Root Port or Endpoint Partner Port > > + * @ide: registered IDE settings descriptor > > + * > > + * When @pdev is a PCI_EXP_TYPE_ENDPOINT then the PCI_IDE_EP partner > > + * settings are written to @pdev's Selective IDE Stream register block, > > + * and when @pdev is a PCI_EXP_TYPE_ROOT_PORT, the PCI_IDE_RP settings > > + * are selected. > > + */ > > +void pci_ide_stream_setup(struct pci_dev *pdev, struct pci_ide *ide) > > +{ > > + struct pci_ide_partner *settings = to_settings(pdev, ide); > > + int pos; > > + u32 val; > > + > > + if (!settings) > > + return; > > + > > + pos = sel_ide_offset(pdev->nr_link_ide, settings->stream_index, > > + pdev->nr_ide_mem); > > > > This and the similar offset caclulation below needs the EXT_CAP_ID_IDE offset *facepalm* So it seems no one is trying to build on top of this framework yet. > > modified drivers/pci/ide.c > @@ -10,11 +10,13 @@ > #include > #include "pci.h" > > -static int sel_ide_offset(int nr_link_ide, int stream_index, int nr_ide_mem) > +static int sel_ide_offset(struct pci_dev *pdev, int nr_link_ide, > + int stream_index, int nr_ide_mem) > { > int offset; > > - offset = PCI_IDE_LINK_STREAM_0 + nr_link_ide * PCI_IDE_LINK_BLOCK_SIZE; > + offset = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_IDE); > + offset += PCI_IDE_LINK_STREAM_0 + nr_link_ide * PCI_IDE_LINK_BLOCK_SIZE; Will fix this up to the following since ide_cap is already cached: static int __sel_ide_offset(int ide_cap, int nr_link_ide, int stream_index, int nr_ide_mem) { int offset; offset = ide_cap + PCI_IDE_LINK_STREAM_0 + nr_link_ide * PCI_IDE_LINK_BLOCK_SIZE; /* * Assume a constant number of address association resources per * stream index */ if (stream_index > 0) offset += stream_index * PCI_IDE_SEL_BLOCK_SIZE(nr_ide_mem); return offset; } static int sel_ide_offset(struct pci_dev *pdev, struct pci_ide_partner *settings) { return sel_ide_offset(pdev->ide_cap, pdev->nr_link_ide, settings->stream_index, pdev->nr_ide_mem); } [..] > > +/** > > + * pci_ide_stream_enable() - after setup, enable the stream > > + * @pdev: PCIe device object for either a Root Port or Endpoint Partner Port > > + * @ide: registered and setup IDE settings descriptor > > + * > > + * Activate the stream by writing to the Selective IDE Stream Control Register. > > + */ > > +void pci_ide_stream_enable(struct pci_dev *pdev, struct pci_ide *ide) > > +{ > > + struct pci_ide_partner *settings = to_settings(pdev, ide); > > + int pos; > > + u32 val; > > + > > + if (!settings) > > + return; > > + > > + pos = sel_ide_offset(pdev->nr_link_ide, settings->stream_index, > > + pdev->nr_ide_mem); > > + > > > > + val = FIELD_PREP(PCI_IDE_SEL_CTL_ID_MASK, ide->stream_id) | > > + FIELD_PREP(PCI_IDE_SEL_CTL_DEFAULT, 1) | > > + FIELD_PREP(PCI_IDE_SEL_CTL_CFG_EN, pdev->ide_cfg) | > > + FIELD_PREP(PCI_IDE_SEL_CTL_TEE_LIMITED, pdev->ide_tee_limit) | > > > > Does enabling pdev->ide_tee_limit here will prevent a device from operating > as expected before we get to TDISP RUN state? My expectation is that non-IDE TLPs can always be sent. I.e. a TDISP device outside the RUN state should still be operational without needing to send T=0 traffic over the IDE stream.