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From: <dan.j.williams@intel.com>
To: Alexey Kardashevskiy <aik@amd.com>, <dan.j.williams@intel.com>,
	<linux-coco@lists.linux.dev>, <linux-pci@vger.kernel.org>
Cc: <linux-kernel@vger.kernel.org>, <bhelgaas@google.com>,
	<lukas@wunner.de>, Samuel Ortiz <sameo@rivosinc.com>,
	Xu Yilun <yilun.xu@linux.intel.com>
Subject: Re: [PATCH v4 04/10] PCI/TSM: Authenticate devices via platform TSM
Date: Mon, 18 Aug 2025 14:08:46 -0700	[thread overview]
Message-ID: <68a3965e9d678_50ce100b@dwillia2-xfh.jf.intel.com.notmuch> (raw)
In-Reply-To: <be66626f-a871-495c-b7fa-42cd3f497245@amd.com>

Alexey Kardashevskiy wrote:
> 
> 
> On 14/8/25 11:40, dan.j.williams@intel.com wrote:
> > Alexey Kardashevskiy wrote:
> >> On 18/7/25 04:33, Dan Williams wrote:
> > [..]
> >>> diff --git a/drivers/pci/tsm.c b/drivers/pci/tsm.c
> >>> new file mode 100644
> >>> index 000000000000..0784cc436dd3
> >>> --- /dev/null
> >>> +++ b/drivers/pci/tsm.c
> > [..]
> >>> +static ssize_t connect_store(struct device *dev, struct device_attribute *attr,
> >>> +			     const char *buf, size_t len)
> >>> +{
> >>> +	struct pci_dev *pdev = to_pci_dev(dev);
> >>> +	const struct pci_tsm_ops *ops;
> >>> +	struct tsm_dev *tsm_dev;
> >>> +	int rc, id;
> >>> +
> >>> +	rc = sscanf(buf, "tsm%d\n", &id);
> >>
> >> Why is id needed here? Are there going to be multiple DSMs per a PCI
> >> device?
> > 
> > The implementation allows for multiple TSMs per platform [1], and you
> > acknowledged this earlier [2] (at least the "no globals" bit).
> > 
> > [1]: http://lore.kernel.org/683f9e141f1b1_1626e1009@dwillia2-xfh.jf.intel.com.notmuch
> 
> Right but I'd think that devices (or, more precisely, PCIe slots) are
> statically assigned to TSMs. A bit hard to imagine 2 TSMs in a system
> and ability to connect some PCI device to either of those. It is not
> impossible but not exactly "painfully simple".

The simple case is the typical case, single TSM. If a platform invents
multiple TSMs then it needs to define a protocol for userspace to figure
out the rules, like "match TSMs to devices by PCIe Segment Number", or
something similar. "Painfully simple" also means not pre-constraining
the ABI just to mitigate future userspace complexity. In the end the
kernel is allowed to not need / have an opinion about this detail.

> > [2]: http://lore.kernel.org/b281b714-5097-4b3a-9809-7bdcb9e004dc@amd.com
> > 
> > One of the nice properties of multiple tsm_devs is the ability to unit test
> > host and guest side TSM flows in the same kernel image.
> > 
> >> I am missing the point of tsm_dev. It does not have sysfs nodes (the
> >> pci_dev parent does)
> > 
> > The resource accounting symlinks for each each IDE stream point to the
> > tsm_dev, see tsm_ide_stream_register().
> > 
> >> tsm_register() takes attribute_group but what would posibbly go there?
> > 
> > Any vendor specific implementation of commonly named attributes.
> > Contrast that with vendor specific attributes with vendor specific names
> > that the vendor specific device publishes.
> > 
> >> certificates/meas/report blobs?
> > 
> > Perhaps.
> 
> Hm. Those groups are per a TSM so no device's certificates/meas/report blobs there, right?

True, I was thinking of a per-device TSM driver supplied attributes
similar to 'struct device_driver'::dev_groups. Both that, and this
@groups parameter to tsm_register() can wait until a solid use case
arrives.

  reply	other threads:[~2025-08-18 21:08 UTC|newest]

Thread overview: 70+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-17 18:33 [PATCH v4 00/10] PCI/TSM: Core infrastructure for PCI device security (TDISP) Dan Williams
2025-07-17 18:33 ` [PATCH v4 01/10] coco/tsm: Introduce a core device for TEE Security Managers Dan Williams
2025-07-29 11:28   ` Jonathan Cameron
2025-07-17 18:33 ` [PATCH v4 02/10] PCI/IDE: Enumerate Selective Stream IDE capabilities Dan Williams
2025-07-29 12:03   ` Jonathan Cameron
2025-08-05 20:59     ` dan.j.williams
2025-08-07 20:12   ` Bjorn Helgaas
2025-08-07 22:37     ` dan.j.williams
2025-08-07 22:53       ` Bjorn Helgaas
2025-08-08  2:17         ` dan.j.williams
2025-08-08 15:59           ` Bjorn Helgaas
2025-08-07 22:43   ` Bjorn Helgaas
2025-07-17 18:33 ` [PATCH v4 03/10] PCI: Introduce pci_walk_bus_reverse(), for_each_pci_dev_reverse() Dan Williams
2025-07-29 13:06   ` Jonathan Cameron
2025-08-05 23:52     ` dan.j.williams
2025-08-06 10:54       ` Jonathan Cameron
2025-08-07 20:24   ` Bjorn Helgaas
2025-08-07 23:17     ` dan.j.williams
2025-08-07 23:26       ` Bjorn Helgaas
2025-07-17 18:33 ` [PATCH v4 04/10] PCI/TSM: Authenticate devices via platform TSM Dan Williams
2025-07-29 14:56   ` Jonathan Cameron
2025-08-06  1:35     ` dan.j.williams
2025-08-06 11:10       ` Jonathan Cameron
2025-08-06 23:16         ` dan.j.williams
2025-08-07 10:42           ` Jonathan Cameron
2025-08-07  2:35         ` dan.j.williams
2025-08-05 15:53   ` Xu Yilun
2025-08-06 22:30     ` dan.j.williams
2025-08-07 21:27   ` Bjorn Helgaas
2025-08-08 22:51     ` dan.j.williams
2025-08-13  2:57   ` Alexey Kardashevskiy
2025-08-14  1:40     ` dan.j.williams
2025-08-14 14:52       ` Alexey Kardashevskiy
2025-08-18 21:08         ` dan.j.williams [this message]
2025-07-17 18:33 ` [PATCH v4 05/10] samples/devsec: Introduce a PCI device-security bus + endpoint sample Dan Williams
2025-07-29 15:16   ` Jonathan Cameron
2025-08-06  3:20     ` dan.j.williams
2025-08-06 11:16       ` Jonathan Cameron
2025-08-06 18:33         ` dan.j.williams
2025-08-11 13:18           ` Gerd Hoffmann
2025-08-11 20:47             ` dan.j.williams
2025-08-07 21:45   ` Bjorn Helgaas
2025-08-08 23:45     ` dan.j.williams
2025-07-17 18:33 ` [PATCH v4 06/10] PCI: Add PCIe Device 3 Extended Capability enumeration Dan Williams
2025-07-29 15:23   ` Jonathan Cameron
2025-08-06 21:00     ` dan.j.williams
2025-08-06 21:02     ` dan.j.williams
2025-08-07 22:06   ` Bjorn Helgaas
2025-08-09  0:05     ` dan.j.williams
2025-08-07 22:46   ` Bjorn Helgaas
2025-07-17 18:33 ` [PATCH v4 07/10] PCI/IDE: Add IDE establishment helpers Dan Williams
2025-07-29 15:45   ` Jonathan Cameron
2025-08-06 21:40     ` dan.j.williams
2025-08-07 22:38   ` Bjorn Helgaas
2025-08-09  1:52     ` dan.j.williams
2025-08-07 22:47   ` Bjorn Helgaas
2025-08-08 10:21   ` Arto Merilainen
2025-08-08 17:26     ` dan.j.williams
2025-08-11  8:02       ` Arto Merilainen
2025-08-28  8:19         ` Aneesh Kumar K.V
2025-07-17 18:33 ` [PATCH v4 08/10] PCI/IDE: Report available IDE streams Dan Williams
2025-07-29 15:47   ` Jonathan Cameron
2025-08-07 22:48   ` Bjorn Helgaas
2025-07-17 18:33 ` [PATCH v4 09/10] PCI/TSM: Report active " Dan Williams
2025-07-29 15:58   ` Jonathan Cameron
2025-08-06 21:55     ` dan.j.williams
2025-08-07 22:49   ` Bjorn Helgaas
2025-07-17 18:33 ` [PATCH v4 10/10] samples/devsec: Add sample IDE establishment Dan Williams
2025-07-29 16:06   ` Jonathan Cameron
2025-07-18 10:57 ` [PATCH v4 00/10] PCI/TSM: Core infrastructure for PCI device security (TDISP) Aneesh Kumar K.V

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