From: <dan.j.williams@intel.com>
To: Alexey Kardashevskiy <aik@amd.com>,
Aneesh Kumar K.V <aneesh.kumar@kernel.org>,
Dan Williams <dan.j.williams@intel.com>,
<linux-coco@lists.linux.dev>, <linux-pci@vger.kernel.org>
Cc: <yilun.xu@linux.intel.com>, <gregkh@linuxfoundation.org>,
Lukas Wunner <lukas@wunner.de>, Samuel Ortiz <sameo@rivosinc.com>,
Bjorn Helgaas <bhelgaas@google.com>
Subject: Re: [PATCH v5 04/10] PCI/TSM: Authenticate devices via platform TSM
Date: Fri, 5 Sep 2025 13:13:23 -0700 [thread overview]
Message-ID: <68bb44634e595_75db10066@dwillia2-mobl4.notmuch> (raw)
In-Reply-To: <8be9cd2d-6a13-40ed-97af-0a6129b2756b@amd.com>
Alexey Kardashevskiy wrote:
>
>
> On 3/9/25 01:13, Aneesh Kumar K.V wrote:
> > Dan Williams <dan.j.williams@intel.com> writes:
> >
> > ....
> >> +
> >> +/**
> >> + * struct pci_tsm - Core TSM context for a given PCIe endpoint
> >> + * @pdev: Back ref to device function, distinguishes type of pci_tsm context
> >> + * @dsm: PCI Device Security Manager for link operations on @pdev
> >> + * @ops: Link Confidentiality or Device Function Security operations
> >> + *
> >> + * This structure is wrapped by low level TSM driver data and returned by
> >> + * probe()/lock(), it is freed by the corresponding remove()/unlock().
> >> + *
> >> + * For link operations it serves to cache the association between a Device
> >> + * Security Manager (DSM) and the functions that manager can assign to a TVM.
> >> + * That can be "self", for assigning function0 of a TEE I/O device, a
> >> + * sub-function (SR-IOV virtual function, or non-function0
> >> + * multifunction-device), or a downstream endpoint (PCIe upstream switch-port as
> >> + * DSM).
> >> + */
> >> +struct pci_tsm {
> >> + struct pci_dev *pdev;
> >> + struct pci_dev *dsm;
> >>
> >
> > struct pci_dev *dsm_dev?
>
> Unless we start calling pci_tsm_pf0 instances "dsm", I'd keep it "dsm".
The per device data for the physical function 0 responsibilities is
called pci_tsm_pf0, the actual device that plays the DSM role in the
TDISP specification is dsm_dev.
> >> + const struct pci_tsm_ops *ops;
> >> +};
> >> +
> >> +/**
> >> + * struct pci_tsm_pf0 - Physical Function 0 TDISP link context
> >> + * @base: generic core "tsm" context
> >> + * @lock: mutual exclustion for pci_tsm_ops invocation
> >> + * @doe_mb: PCIe Data Object Exchange mailbox
> >> + */
> >> +struct pci_tsm_pf0 {
> >> + struct pci_tsm base;
> >>
> >
> > struct pci_tsm base_tsm ?
>
> It is usually pdev->tsm->... so it has "tsm" in the value, having another "tsm" is hardly useful imho.
It only shows up in a few places. I think it is ok.
> >> + struct mutex lock;
> >> + struct pci_doe_mb *doe_mb;
> >> +};
> >> +
> >
> >
> > Both the above will help when we have names likes
> >
> > dsm->pci.base.pdev; vs dsm->pci.base_tsm.pdev;
>
> What type this "dsm" of in this example? Currently it is pci_dev which has no "pci" member. Thanks,
True, not sure what Aneesh was thinking here, but that does not really
change my view of the above renames.
I do want to stop spinning this patch based on trivial naming issues. I
think at this point everyone has had a chance to weigh in with their
preferences. I know I have picked up some from you, Aneesh, and Yilun
against my first choice.
Let's please stop quibbling with the names post v6 unless Bjorn raises a
specific concern.
next prev parent reply other threads:[~2025-09-05 20:13 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-27 3:51 [PATCH v5 00/10] PCI/TSM: Core infrastructure for PCI device security (TDISP) Dan Williams
2025-08-27 3:51 ` [PATCH v5 01/10] coco/tsm: Introduce a core device for TEE Security Managers Dan Williams
2025-08-27 3:51 ` [PATCH v5 02/10] PCI/IDE: Enumerate Selective Stream IDE capabilities Dan Williams
2025-09-15 16:18 ` Jonathan Cameron
2025-09-19 23:32 ` dan.j.williams
2025-08-27 3:51 ` [PATCH v5 03/10] PCI: Introduce pci_walk_bus_reverse(), for_each_pci_dev_reverse() Dan Williams
2025-08-27 3:51 ` [PATCH v5 04/10] PCI/TSM: Authenticate devices via platform TSM Dan Williams
2025-08-27 13:25 ` Alexey Kardashevskiy
2025-08-29 1:06 ` dan.j.williams
2025-08-29 1:58 ` Alexey Kardashevskiy
2025-09-05 0:50 ` dan.j.williams
2025-09-05 3:34 ` Alexey Kardashevskiy
2025-09-06 2:07 ` dan.j.williams
2025-09-08 6:13 ` Alexey Kardashevskiy
2025-09-09 0:41 ` dan.j.williams
2025-09-09 1:35 ` Alexey Kardashevskiy
2025-09-09 1:52 ` dan.j.williams
2025-09-10 10:55 ` Alexey Kardashevskiy
2025-09-10 15:45 ` dan.j.williams
2025-08-28 11:43 ` Alexey Kardashevskiy
2025-08-29 1:23 ` dan.j.williams
2025-08-30 13:26 ` Alexey Kardashevskiy
2025-09-05 0:51 ` dan.j.williams
2025-09-02 15:08 ` Aneesh Kumar K.V
2025-09-03 2:03 ` Alexey Kardashevskiy
2025-09-05 20:06 ` dan.j.williams
2025-09-05 19:13 ` dan.j.williams
2025-09-02 15:13 ` Aneesh Kumar K.V
2025-09-03 2:07 ` Alexey Kardashevskiy
2025-09-05 20:13 ` dan.j.williams [this message]
2025-09-08 11:19 ` Alexey Kardashevskiy
2025-09-05 20:03 ` dan.j.williams
2025-09-03 2:17 ` Alexey Kardashevskiy
2025-09-05 20:35 ` dan.j.williams
2025-08-27 3:51 ` [PATCH v5 05/10] samples/devsec: Introduce a PCI device-security bus + endpoint sample Dan Williams
2025-08-27 3:51 ` [PATCH v5 06/10] PCI: Add PCIe Device 3 Extended Capability enumeration Dan Williams
2025-08-27 3:51 ` [PATCH v5 07/10] PCI/IDE: Add IDE establishment helpers Dan Williams
2025-09-02 1:29 ` Alexey Kardashevskiy
2025-09-02 1:54 ` Alexey Kardashevskiy
2025-09-05 1:40 ` dan.j.williams
2025-09-05 2:14 ` Alexey Kardashevskiy
2025-09-06 2:00 ` dan.j.williams
2025-09-08 6:25 ` Alexey Kardashevskiy
2025-09-09 0:42 ` dan.j.williams
2025-09-15 11:46 ` Alexey Kardashevskiy
2025-10-17 4:06 ` Alexey Kardashevskiy
2025-10-17 4:40 ` dan.j.williams
2025-10-17 11:15 ` Alexey Kardashevskiy
2025-09-05 1:27 ` dan.j.williams
2025-09-05 2:23 ` Alexey Kardashevskiy
2025-10-17 11:31 ` Alexey Kardashevskiy
2025-10-17 19:18 ` dan.j.williams
2025-10-28 23:00 ` dan.j.williams
2025-10-29 8:04 ` Alexey Kardashevskiy
2025-08-27 3:51 ` [PATCH v5 08/10] PCI/IDE: Report available IDE streams Dan Williams
2025-08-27 3:51 ` [PATCH v5 09/10] PCI/TSM: Report active " Dan Williams
2025-08-27 3:51 ` [PATCH v5 10/10] samples/devsec: Add sample IDE establishment Dan Williams
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=68bb44634e595_75db10066@dwillia2-mobl4.notmuch \
--to=dan.j.williams@intel.com \
--cc=aik@amd.com \
--cc=aneesh.kumar@kernel.org \
--cc=bhelgaas@google.com \
--cc=gregkh@linuxfoundation.org \
--cc=linux-coco@lists.linux.dev \
--cc=linux-pci@vger.kernel.org \
--cc=lukas@wunner.de \
--cc=sameo@rivosinc.com \
--cc=yilun.xu@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).