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From: <dan.j.williams@intel.com>
To: Jonathan Cameron <jonathan.cameron@huawei.com>,
	Dan Williams <dan.j.williams@intel.com>
Cc: <linux-coco@lists.linux.dev>, <linux-pci@vger.kernel.org>,
	<yilun.xu@linux.intel.com>, <aneesh.kumar@kernel.org>,
	<aik@amd.com>, <gregkh@linuxfoundation.org>
Subject: Re: [PATCH v5 02/10] PCI/IDE: Enumerate Selective Stream IDE capabilities
Date: Fri, 19 Sep 2025 16:32:19 -0700	[thread overview]
Message-ID: <68cde80323710_105201001e@dwillia2-mobl4.notmuch> (raw)
In-Reply-To: <20250915171810.00003212@huawei.com>

Jonathan Cameron wrote:
> On Tue, 26 Aug 2025 20:51:18 -0700
> Dan Williams <dan.j.williams@intel.com> wrote:
> 
> > Link encryption is a new PCIe feature enumerated by "PCIe r7.0 section
> > 7.9.26 IDE Extended Capability".
> > 
> > It is both a standalone port + endpoint capability, and a building block
> > for the security protocol defined by "PCIe r7.0 section 11 TEE Device
> > Interface Security Protocol (TDISP)". That protocol coordinates device
> > security setup between a platform TSM (TEE Security Manager) and a
> > device DSM (Device Security Manager). While the platform TSM can
> > allocate resources like Stream ID and manage keys, it still requires
> > system software to manage the IDE capability register block.
> > 
> > Add register definitions and basic enumeration in preparation for
> > Selective IDE Stream establishment. A follow on change selects the new
> > CONFIG_PCI_IDE symbol. Note that while the IDE specification defines
> > both a point-to-point "Link Stream" and a Root Port to endpoint
> > "Selective Stream", only "Selective Stream" is considered for Linux as
> > that is the predominant mode expected by Trusted Execution Environment
> > Security Managers (TSMs), and it is the security model that limits the
> > number of PCI components within the TCB in a PCIe topology with
> > switches.
> > 
> > Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > Cc: Aneesh Kumar K.V <aneesh.kumar@kernel.org>
> > Co-developed-by: Alexey Kardashevskiy <aik@amd.com>
> > Signed-off-by: Alexey Kardashevskiy <aik@amd.com>
> > Co-developed-by: Xu Yilun <yilun.xu@linux.intel.com>
> > Signed-off-by: Xu Yilun <yilun.xu@linux.intel.com>
> > Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> 
> Some very very trivial things inline.
> 
> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
> 
> 
> 
> > diff --git a/drivers/pci/ide.c b/drivers/pci/ide.c
> > new file mode 100644
> > index 000000000000..05ab8c18b768
> > --- /dev/null
> > +++ b/drivers/pci/ide.c
> > @@ -0,0 +1,92 @@
> 
> > +void pci_ide_init(struct pci_dev *pdev)
> > +{
> > +	u8 nr_link_ide, nr_ide_mem, nr_streams;
> > +	u16 ide_cap;
> > +	u32 val;
> > +
> > +	if (!pci_is_pcie(pdev))
> > +		return;
> > +
> > +	ide_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_IDE);
> > +	if (!ide_cap)
> > +		return;
> > +
> > +	pci_read_config_dword(pdev, ide_cap + PCI_IDE_CAP, &val);
> > +	if ((val & PCI_IDE_CAP_SELECTIVE) == 0)
> > +		return;
> > +
> > +	/*
> > +	 * Require endpoint IDE capability to be paired with IDE Root
> > +	 * Port IDE capability.
> > +	 */
> > +	if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ENDPOINT) {
> > +		struct pci_dev *rp = pcie_find_root_port(pdev);
> > +
> > +		if (!rp->ide_cap)
> > +			return;
> > +	}
> > +
> > +	if (val & PCI_IDE_CAP_SEL_CFG)
> > +		pdev->ide_cfg = 1;
> > +
> > +	if (val & PCI_IDE_CAP_TEE_LIMITED)
> > +		pdev->ide_tee_limit = 1;
> > +
> > +	if (val & PCI_IDE_CAP_LINK)
> > +		nr_link_ide = 1 + FIELD_GET(PCI_IDE_CAP_LINK_TC_NUM, val);
> > +	else
> > +		nr_link_ide = 0;
> > +
> > +	nr_ide_mem = 0;
> > +	nr_streams = min(1 + FIELD_GET(PCI_IDE_CAP_SEL_NUM, val),
> > +			 CONFIG_PCI_IDE_STREAM_MAX);
> > +	for (u8 i = 0; i < nr_streams; i++) {
> > +		int pos = __sel_ide_offset(ide_cap, nr_link_ide, i, nr_ide_mem);
> > +		int nr_assoc;
> > +		u32 val;
> > +
> > +		pci_read_config_dword(pdev, pos, &val);
> > +
> > +		/*
> > +		 * Let's not entertain streams that do not have a
> > +		 * constant number of address association blocks
> constant fits on the line above and I can't immediately see a reason
> to wrap early.

Now I understand the "very very". So in this case this change destroys
"git patch-id --stable" and in this new age of Link: being deprecated
resending this to the list feels not worth it to me.

> > +
> > +/* Selective IDE Stream block, up to PCI_IDE_CAP_SELECTIVE_STREAMS_NUM */
> > +/* Selective IDE Stream Capability Register */
> > +#define  PCI_IDE_SEL_CAP		0x00
> > +#define  PCI_IDE_SEL_CAP_ASSOC_NUM	__GENMASK(3, 0)
> 
> This one is a field so one more space needed

This fixup preserves git patch-id, done.

  reply	other threads:[~2025-09-19 23:32 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-27  3:51 [PATCH v5 00/10] PCI/TSM: Core infrastructure for PCI device security (TDISP) Dan Williams
2025-08-27  3:51 ` [PATCH v5 01/10] coco/tsm: Introduce a core device for TEE Security Managers Dan Williams
2025-08-27  3:51 ` [PATCH v5 02/10] PCI/IDE: Enumerate Selective Stream IDE capabilities Dan Williams
2025-09-15 16:18   ` Jonathan Cameron
2025-09-19 23:32     ` dan.j.williams [this message]
2025-08-27  3:51 ` [PATCH v5 03/10] PCI: Introduce pci_walk_bus_reverse(), for_each_pci_dev_reverse() Dan Williams
2025-08-27  3:51 ` [PATCH v5 04/10] PCI/TSM: Authenticate devices via platform TSM Dan Williams
2025-08-27 13:25   ` Alexey Kardashevskiy
2025-08-29  1:06     ` dan.j.williams
2025-08-29  1:58       ` Alexey Kardashevskiy
2025-09-05  0:50         ` dan.j.williams
2025-09-05  3:34           ` Alexey Kardashevskiy
2025-09-06  2:07             ` dan.j.williams
2025-09-08  6:13               ` Alexey Kardashevskiy
2025-09-09  0:41                 ` dan.j.williams
2025-09-09  1:35                   ` Alexey Kardashevskiy
2025-09-09  1:52                     ` dan.j.williams
2025-09-10 10:55                       ` Alexey Kardashevskiy
2025-09-10 15:45                         ` dan.j.williams
2025-08-28 11:43   ` Alexey Kardashevskiy
2025-08-29  1:23     ` dan.j.williams
2025-08-30 13:26   ` Alexey Kardashevskiy
2025-09-05  0:51     ` dan.j.williams
2025-09-02 15:08   ` Aneesh Kumar K.V
2025-09-03  2:03     ` Alexey Kardashevskiy
2025-09-05 20:06       ` dan.j.williams
2025-09-05 19:13     ` dan.j.williams
2025-09-02 15:13   ` Aneesh Kumar K.V
2025-09-03  2:07     ` Alexey Kardashevskiy
2025-09-05 20:13       ` dan.j.williams
2025-09-08 11:19         ` Alexey Kardashevskiy
2025-09-05 20:03     ` dan.j.williams
2025-09-03  2:17   ` Alexey Kardashevskiy
2025-09-05 20:35     ` dan.j.williams
2025-08-27  3:51 ` [PATCH v5 05/10] samples/devsec: Introduce a PCI device-security bus + endpoint sample Dan Williams
2025-08-27  3:51 ` [PATCH v5 06/10] PCI: Add PCIe Device 3 Extended Capability enumeration Dan Williams
2025-08-27  3:51 ` [PATCH v5 07/10] PCI/IDE: Add IDE establishment helpers Dan Williams
2025-09-02  1:29   ` Alexey Kardashevskiy
2025-09-02  1:54     ` Alexey Kardashevskiy
2025-09-05  1:40       ` dan.j.williams
2025-09-05  2:14         ` Alexey Kardashevskiy
2025-09-06  2:00           ` dan.j.williams
2025-09-08  6:25             ` Alexey Kardashevskiy
2025-09-09  0:42               ` dan.j.williams
2025-09-15 11:46             ` Alexey Kardashevskiy
2025-09-05  1:27     ` dan.j.williams
2025-09-05  2:23       ` Alexey Kardashevskiy
2025-08-27  3:51 ` [PATCH v5 08/10] PCI/IDE: Report available IDE streams Dan Williams
2025-08-27  3:51 ` [PATCH v5 09/10] PCI/TSM: Report active " Dan Williams
2025-08-27  3:51 ` [PATCH v5 10/10] samples/devsec: Add sample IDE establishment Dan Williams

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