Re: [PATCH v2] PCI/IDE: Add Address Association Register setup for downstream MMIO

[<dan.j.williams@intel.com>]

Xu Yilun wrote:
> Add Address Association Register setup for downstream MMIO
> 
> The address ranges for RP side Address Association Registers should
> cover memory addresses for all PFs/VFs/downstream devices of the DSM
> device. A simple solution is to get the aggregated memory range and
> prefetchable-memory range from directly connected downstream port
> (either an RP or a switch port) and set into 2 Address Association
> Register blocks.
> 
> Just like RID association, address associations will be set by default
> if hardware sets 'Number of Address Association Register Blocks' in the
> 'Selective IDE Stream Capability Register' to a non-zero value.
> Alternatively, TSM drivers can opt-out of the settings by zero'ing out
> the probed region.
> 
> If the directly connected downstream port provides both memory range
> and prefetchable-memory range but the platform only provides 1 Address
> Association Register block then setup the former first. This follows the
> PCI bridge specification precedent where memory is mandatory and
> prefetchable-memory is optional. Priortize the mandatory one. If the
> platform can't fit into the default setup, TSM drivers can always change
> the setting before setup. E.g. zero'ing out the memory range so that
> prefetchable-memory range could be setup.
> 
> The Address Association Register setup for Endpoint Side is still
> uncertain so isn't supported in this patch.

This looks good Yilun. I will append it to the end of the v7 posting of
the PCI/TSM base series.

I will likely split the resource_assigned() introduction to its own
patch with a Link: to the rationale provided by Ilpo, and perform some
other small fixups. Like I notice I defined the rid registers as rid_X
and the address association registers as assocX, so I'll drop the "_".