Re: [PATCH v7 2/9] PCI/IDE: Enumerate Selective Stream IDE capabilities

[<dan.j.williams@intel.com>]

Alexey Kardashevskiy wrote:
[..]
> > +/* Integrity and Data Encryption Extended Capability */
> > +#define PCI_IDE_CAP			0x04
> > +#define  PCI_IDE_CAP_LINK		0x1  /* Link IDE Stream Supported */
> > +#define  PCI_IDE_CAP_SELECTIVE		0x2  /* Selective IDE Streams Supported */
> > +#define  PCI_IDE_CAP_FLOWTHROUGH	0x4  /* Flow-Through IDE Stream Supported */
> > +#define  PCI_IDE_CAP_PARTIAL_HEADER_ENC 0x8  /* Partial Header Encryption Supported */
> > +#define  PCI_IDE_CAP_AGGREGATION	0x10 /* Aggregation Supported */
> > +#define  PCI_IDE_CAP_PCRC		0x20 /* PCRC Supported */
> > +#define  PCI_IDE_CAP_IDE_KM		0x40 /* IDE_KM Protocol Supported */
> > +#define  PCI_IDE_CAP_SEL_CFG		0x80 /* Selective IDE for Config Request Support */
> > +#define  PCI_IDE_CAP_ALG		__GENMASK(12, 8) /* Supported Algorithms */
> > +#define   PCI_IDE_CAP_ALG_AES_GCM_256	0    /* AES-GCM 256 key size, 96b MAC */
> > +#define  PCI_IDE_CAP_LINK_TC_NUM	__GENMASK(15, 13) /* Link IDE TCs */
> > +#define  PCI_IDE_CAP_SEL_NUM		__GENMASK(23, 16) /* Supported Selective IDE Streams */
> > +#define  PCI_IDE_CAP_TEE_LIMITED	0x1000000 /* TEE-Limited Stream Supported */
> 
> 
> Since you are referring to PCIe r7.0 (instead of my proposal to use
> r6.1 ;) ), it has XT now here and in the stream control registers.

Recall that Bjorn asked for the s/r6.1/r7.0/ conversion throughout.

> I posted a patch for lspci with this:
> https://lore.kernel.org/r/20251023071101.578312-1-aik@amd.com

I think we should handle XT support the same way for the kernel, i.e.
with a follow-on patch.

> Otherwise
> 
> Reviewed-by: Alexey Kardashevskiy <aik@amd.com>

Thanks!