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With those descriptors the TSM driver can use pci_tsm_mmio_setup() to > inform ioremap() how to map the device per the device's expectations. The > VM is expected to validate the interface with the relying party before > accepting the device for operation. > > The helper also provides the obfuscated starting address for each encrypted > MMIO range as the VM is never disclosed on the hpa that correlates to the > gpa of the device's mmio. The obfuscated address is BAR aligned. > > Based on an original patch by Aneesh [1] > > Cc: Arnd Bergmann > Link: https://lore.kernel.org/linux-coco/20251117140007.122062-8-aneesh.kumar@kernel.org/ [1] > Co-developed-by: Xu Yilun > Signed-off-by: Xu Yilun > Signed-off-by: Dan Williams > --- > include/linux/ioport.h | 2 + > include/linux/pci-tsm.h | 35 +++++++ > drivers/pci/tsm/core.c | 224 ++++++++++++++++++++++++++++++++++++++++ > kernel/resource.c | 8 ++ > 4 files changed, 269 insertions(+) > > diff --git a/include/linux/ioport.h b/include/linux/ioport.h > index f7930b3dfd0a..122f1eefb4b9 100644 > --- a/include/linux/ioport.h > +++ b/include/linux/ioport.h > @@ -144,6 +144,7 @@ enum { > IORES_DESC_RESERVED = 7, > IORES_DESC_SOFT_RESERVED = 8, > IORES_DESC_CXL = 9, > + IORES_DESC_ENCRYPTED = 10, > }; > > /* > @@ -240,6 +241,7 @@ struct resource_constraint { > extern struct resource ioport_resource; > extern struct resource iomem_resource; > extern struct resource soft_reserve_resource; > +extern struct resource encrypted_iomem_resource; > > extern struct resource *request_resource_conflict(struct resource *root, struct resource *new); > extern int request_resource(struct resource *root, struct resource *new); > diff --git a/include/linux/pci-tsm.h b/include/linux/pci-tsm.h > index 397e5d8459cb..6d5fadd79360 100644 > --- a/include/linux/pci-tsm.h > +++ b/include/linux/pci-tsm.h > @@ -156,12 +156,42 @@ struct pci_tsm_pf0 { > struct pci_doe_mb *doe_mb; > }; > > +/** > + * struct pci_tsm_mmio_entry - an encrypted MMIO range > + * @res: MMIO address range (typically Guest Physical Address, GPA) > + * @tsm_offset: Host Physical Address, HPA obfuscation offset added by the TSM. > + * Translates report addresses to GPA. > + */ > +struct pci_tsm_mmio_entry { > + struct resource res; > + u64 tsm_offset; > +}; > + > +struct pci_tsm_mmio { > + int nr; > + struct pci_tsm_mmio_entry mmio[]; > +}; > + > +static inline struct pci_tsm_mmio_entry * > +pci_tsm_mmio_entry(struct pci_tsm_mmio *mmio, int idx) > +{ > + return &mmio->mmio[idx]; > +} > + > +static inline struct resource *pci_tsm_mmio_resource(struct pci_tsm_mmio *mmio, > + int idx) > +{ > + return &mmio->mmio[idx].res; > +} > + > /** > * struct pci_tsm_devsec - context for tracking private/accepted PCI resources > * @base_tsm: generic core "tsm" context > + * @mmio: encrypted MMIO resources for this assigned device > */ > struct pci_tsm_devsec { > struct pci_tsm base_tsm; > + struct pci_tsm_mmio *mmio; > }; > > /* physical function0 and capable of 'connect' */ > @@ -263,6 +293,11 @@ static inline const struct pci_tsm_ops *to_pci_tsm_ops(struct pci_tsm *tsm) > return tsm->tsm_dev->pci_ops; > } > struct pci_tsm_devsec *to_pci_tsm_devsec(struct pci_tsm *tsm); > +int pci_tsm_mmio_setup(struct pci_dev *pdev, struct pci_tsm_mmio *mmio); > +void pci_tsm_mmio_teardown(struct pci_tsm_mmio *mmio); > + > +struct pci_tsm_mmio *pci_tsm_mmio_alloc(struct pci_dev *pdev); > +int pci_tsm_mmio_free(struct pci_dev *pdev, struct pci_tsm_mmio *mmio); > #else > static inline int pci_tsm_register(struct tsm_dev *tsm_dev) > { > diff --git a/drivers/pci/tsm/core.c b/drivers/pci/tsm/core.c > index 372363a39a44..9ac216ad896d 100644 > --- a/drivers/pci/tsm/core.c > +++ b/drivers/pci/tsm/core.c > @@ -15,6 +15,7 @@ > #include > #include > #include > +#include > #include > #include "../pci.h" > > @@ -552,6 +553,229 @@ static ssize_t dsm_show(struct device *dev, struct device_attribute *attr, > } > static DEVICE_ATTR_RO(dsm); > > +static void mmio_teardown(struct pci_tsm_mmio *mmio, int nr) > +{ > + while (nr--) > + remove_resource(pci_tsm_mmio_resource(mmio, nr)); > +} > + > +/** > + * pci_tsm_mmio_setup() - mark device MMIO as encrypted in iomem > + * @pdev: device owner of MMIO resources > + * @mmio: container of an array of resources to mark encrypted > + */ > +int pci_tsm_mmio_setup(struct pci_dev *pdev, struct pci_tsm_mmio *mmio) > +{ > + int i; > + > + device_lock_assert(&pdev->dev); > + if (pdev->dev.driver) > + return -EBUSY; > + > + for (i = 0; i < mmio->nr; i++) { > + struct resource *res = pci_tsm_mmio_resource(mmio, i); > + int j; > + > + if (resource_size(res) == 0 || !res->end) > + break; > + > + /* Only require the caller to set the range, init remainder */ > + *res = DEFINE_RES_NAMED_DESC(res->start, resource_size(res), > + pci_name(pdev), IORESOURCE_MEM, > + IORES_DESC_ENCRYPTED); > + > + for (j = 0; j < PCI_NUM_RESOURCES; j++) > + if (resource_contains(pci_resource_n(pdev, j), res)) > + break; > + > + /* Request is outside of device MMIO */ > + if (j >= PCI_NUM_RESOURCES) > + break; > + > + if (insert_resource(&encrypted_iomem_resource, res) != 0) > + break; > + } > + > + if (i >= mmio->nr) > + return 0; > + > + mmio_teardown(mmio, i); > + > + return -EINVAL; > +} > +EXPORT_SYMBOL_GPL(pci_tsm_mmio_setup); > + > +void pci_tsm_mmio_teardown(struct pci_tsm_mmio *mmio) > +{ > + mmio_teardown(mmio, mmio->nr); > +} > +EXPORT_SYMBOL_GPL(pci_tsm_mmio_teardown); > + > +/* > + * PCIe ECN TEE Device Interface Security Protocol (TDISP) > + * > + * Device Interface Report data object layout as defined by PCIe r7.0 section > + * 11.3.11 > + */ > +#define PCI_TSM_DEVIF_REPORT_MMIO_ATTR_MSIX_TABLE BIT(0) > +#define PCI_TSM_DEVIF_REPORT_MMIO_ATTR_MSIX_PBA BIT(1) > +#define PCI_TSM_DEVIF_REPORT_MMIO_ATTR_IS_NON_TEE BIT(2) > +#define PCI_TSM_DEVIF_REPORT_MMIO_ATTR_IS_UPDATABLE BIT(3) > +#define PCI_TSM_DEVIF_REPORT_MMIO_ATTR_RANGE_ID GENMASK(31, 16) > + > +/* An interface report 'pfn' is 4K in size */ > +struct pci_tsm_devif_mmio { > + __le64 phys; > + __le32 nr_pfns; > + __le32 attributes; > +}; > + > +struct pci_tsm_devif_report { > + __le16 interface_info; > + __le16 reserved; > + __le16 msi_x_message_control; > + __le16 lnr_control; > + __le32 tph_control; > + __le32 mmio_range_count; > + struct pci_tsm_devif_mmio mmio[]; > +}; > + > +/** > + * pci_tsm_mmio_alloc() - allocate encrypted MMIO range descriptor > + * @pdev: device owner of MMIO ranges > + * > + * Return: the encrypted MMIO range descriptor on success, NULL on failure > + * > + * Assumes that this is called within the live lifetime of a PCI device's > + * association with a low level TSM. > + */ > +struct pci_tsm_mmio *pci_tsm_mmio_alloc(struct pci_dev *pdev) > +{ > + struct device_evidence *evidence = pdev->tsm->evidence; > + u64 reporting_bar_base, last_reporting_end; > + struct device_evidence_object *report_obj; > + const struct pci_tsm_devif_report *report; > + u32 mmio_range_count; > + int last_bar = -1; > + int i; > + > + if (!evidence) > + return NULL; > + > + report_obj = &evidence->obj[DEVICE_EVIDENCE_TYPE_REPORT]; > + > + guard(rwsem_read)(&evidence->lock); > + if (report_obj->len < sizeof(struct pci_tsm_devif_report)) > + return NULL; > + > + report = report_obj->data; > + mmio_range_count = __le32_to_cpu(report->mmio_range_count); > + > + /* check that the report object is self-consistent on mmio entries */ > + if (report_obj->len < struct_size(report, mmio, mmio_range_count)) > + return NULL; > + > + /* create pci_tsm_mmio descriptors from the report data */ > + struct pci_tsm_mmio *mmio __free(kfree) = > + kzalloc_flex(*mmio, mmio, mmio_range_count); > + if (!mmio) > + return NULL; > + > + for (i = 0; i < mmio_range_count; i++) { > + u64 range_off; > + struct range range; > + const struct pci_tsm_devif_mmio *mmio_data = &report->mmio[i]; > + struct pci_tsm_mmio_entry *entry = > + pci_tsm_mmio_entry(mmio, mmio->nr); > + u64 tsm_offset = __le64_to_cpu(mmio_data->phys); * SZ_4K is missing. > + u64 size = __le32_to_cpu(mmio_data->nr_pfns) * SZ_4K; > + u32 attr = __le32_to_cpu(mmio_data->attributes); > + int bar = FIELD_GET(PCI_TSM_DEVIF_REPORT_MMIO_ATTR_RANGE_ID, > + attr); > + > + if (bar >= PCI_STD_NUM_BARS || > + !(pci_resource_flags(pdev, bar) & IORESOURCE_MEM) || > + (pci_resource_flags(pdev, bar) & IORESOURCE_UNSET)) { > + pci_dbg(pdev, "Invalid reporting bar ID %d\n", bar); > + return NULL; > + } > + > + if (last_bar > bar) { > + pci_dbg(pdev, "Reporting bar ID not in ascending order\n"); > + return NULL; > + } > + > + if (last_bar < bar) { > + unsigned long mask = pci_resource_len(pdev, bar) - 1; > + > + /* Transition to a new bar */ > + last_bar = bar; > + > + /* > + * Determine the obfuscated base of the BAR. BAR > + * offsets are never obfuscated. > + */ > + reporting_bar_base = tsm_offset & ~mask; > + } else if (tsm_offset < last_reporting_end) { > + pci_dbg(pdev, "Reporting ranges within BAR not in ascending order\n"); > + return NULL; > + } > + > + /* Per spec the tsm_offset never results in overflow / underflow */ > + last_reporting_end = tsm_offset + size; > + if (last_reporting_end < tsm_offset) { > + pci_dbg(pdev, "Reporting range overflow\n"); > + return NULL; > + } > + > + range_off = tsm_offset - reporting_bar_base; If we all do the mmio_reporting_offset in the same way (use the bar size low bits), then this can be simplified and should be as it does not account for the non-locked (==not reported) MSIX anyway. Thanks, > + if (pci_resource_len(pdev, bar) < range_off + size) { > + pci_dbg(pdev, "Reporting range larger than BAR size\n"); > + return NULL; > + } > + > + range.start = pci_resource_start(pdev, bar) + range_off; > + range.end = range.start + size - 1; > + > + /* Only record the TEE ranges for later consideration by ioremap() */ > + if (FIELD_GET(PCI_TSM_DEVIF_REPORT_MMIO_ATTR_IS_NON_TEE, > + attr)) { > + pci_dbg(pdev, "Skipping non-TEE range, BAR%d %pra\n", > + bar, &range); > + continue; > + } > + > + entry->res.start = range.start; > + entry->res.end = range.end; > + entry->tsm_offset = tsm_offset; > + mmio->nr++; > + } > + > + return_ptr(mmio); > +} > +EXPORT_SYMBOL_GPL(pci_tsm_mmio_alloc); > + > +/** > + * pci_tsm_mmio_free() - free a pci_tsm_mmio instance > + * @pdev: device owner of MMIO ranges > + * @mmio: instance to free > + * > + * Returns 0 if @mmio was idle on entry, -EBUSY otherwise > + */ > +int pci_tsm_mmio_free(struct pci_dev *pdev, struct pci_tsm_mmio *mmio) > +{ > + for (int i = 0; i < mmio->nr; i++) { > + struct resource *res = pci_tsm_mmio_resource(mmio, i); > + > + if (dev_WARN_ONCE(&pdev->dev, resource_assigned(res), > + "MMIO resource still assigned %pr\n", res)) > + return -EBUSY; > + } > + kfree(mmio); > + return 0; > +} > +EXPORT_SYMBOL_GPL(pci_tsm_mmio_free); > + > /** > * pci_tsm_accept() - accept a device for private MMIO operation > * @pdev: PCI device to accept > diff --git a/kernel/resource.c b/kernel/resource.c > index 3d17e3196a3e..ba91ce43ff7a 100644 > --- a/kernel/resource.c > +++ b/kernel/resource.c > @@ -56,6 +56,14 @@ struct resource soft_reserve_resource = { > .flags = IORESOURCE_MEM, > }; > > +struct resource encrypted_iomem_resource = { > + .name = "Encrypted MMIO", > + .start = 0, > + .end = -1, > + .desc = IORES_DESC_ENCRYPTED, > + .flags = IORESOURCE_MEM, > +}; > + > static DEFINE_RWLOCK(resource_lock); > > /* -- Alexey