From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65DCB72 for ; Tue, 10 Aug 2021 19:23:57 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10072"; a="211867456" X-IronPort-AV: E=Sophos;i="5.84,310,1620716400"; d="scan'208";a="211867456" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Aug 2021 12:23:50 -0700 X-IronPort-AV: E=Sophos;i="5.84,310,1620716400"; d="scan'208";a="515958752" Received: from akleen-mobl1.amr.corp.intel.com (HELO [10.209.69.62]) ([10.209.69.62]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Aug 2021 12:23:49 -0700 Subject: Re: [PATCH 1/5] mm: Add support for unaccepted memory To: Dave Hansen , "Kirill A. Shutemov" , Borislav Petkov , Andy Lutomirski , Sean Christopherson , Andrew Morton , Joerg Roedel Cc: Kuppuswamy Sathyanarayanan , David Rientjes , Vlastimil Babka , Tom Lendacky , Thomas Gleixner , Peter Zijlstra , Paolo Bonzini , Ingo Molnar , Varad Gautam , Dario Faggioli , x86@kernel.org, linux-mm@kvack.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" References: <20210810062626.1012-1-kirill.shutemov@linux.intel.com> <20210810062626.1012-2-kirill.shutemov@linux.intel.com> <9748c07c-4e59-89d0-f425-c57f778d1b42@linux.intel.com> <17b6a3a3-bd7d-f57e-8762-96258b16247a@intel.com> From: Andi Kleen Message-ID: <796a4b20-7fa3-3086-efa0-2f728f35ae06@linux.intel.com> Date: Tue, 10 Aug 2021 12:23:48 -0700 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.12.0 Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In-Reply-To: <17b6a3a3-bd7d-f57e-8762-96258b16247a@intel.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US > But, not everyone is going to agree with me. Both the Intel TDX and the AMD SEV side independently came to opposite conclusions. In general people care a lot about boot time of VM guests. > > This also begs the question of how folks know when this "blip" is over. > Do we have a counter for offline pages? Is there any way to force page > acceptance? Or, are we just stuck allocating a bunch of memory to warm > up the system? > > How do folks who care about these new blips avoid them? It's not different than any other warmup. At warmup time you always have lots of blips until the working set stabilizes. For example in virtualization first touch of a new page is usually an EPT violation handled to the host. Or in the native case you may need to do IO or free memory. Everybody who based their critical latency percentiles around a warming up process would be foolish, the picture would be completely distorted. So the basic operation is adding some overhead, but I don't think anything is that unusual compared to the state of the art. Now perhaps the locking might be a problem if the other operations all run in parallel, causing unnecessary serialization If that's really a problem I guess we can optimize later. I don't think there's anything fundamental about the current locking. -Andi