From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C12DA339716 for ; Mon, 5 Jan 2026 17:19:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767633558; cv=none; b=DWWPE3chcDhmx7XF+wSHye5VGrwz0nYIBDC3o6xf2OyfZxL20A4ujJqEkwJUqw2b+LUSpZ6R2K5yszDnEAWlEBhKASYBIbEz4M3jCOUoc/CbxUnqiMQ7SkD/IXQwRgbSdGS9JV4emcbHDYa9ofQgKqGr3TLRKfFx2fmqewPeF2U= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767633558; c=relaxed/simple; bh=w1WedrajXazIUVprYcnvt8REd4ctbM7lgWDFK/DTBNM=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=YwZjcRhkFjyb4dSf5H4HlezxubT8hakw/3y4n/ktk7hQ7tbCIwmfLc3OIljPDwDtp7oGO0UEtlnj3YIvvRhcJcNEOyIEVHPW54e7S31UToT+XHVK+0PJcS63FTq3dkBiDjIJDfYrxxCWEeBcQEN9VfFpQaonbdq21wcW/gXhvX0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=dBvbh/tP; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="dBvbh/tP" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1767633555; x=1799169555; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=w1WedrajXazIUVprYcnvt8REd4ctbM7lgWDFK/DTBNM=; b=dBvbh/tP96Kjgw+lTH+HMYDyQHku60qF9Ah4A+rRhjnPpO6Q2f3B31pN q7MBXLzLTj9Osfgsn8vDTu1tWLDUx+ea9pfAizuLYww9ujqZnYMdQ+p0a 5MZ/KWdUzkot4eUmpmKW4MbHcBBdkgV8CZ2ITUCq0WzlNXj0Kop3V9NXw fCS+MopJaHgOn9HzSQMW1qC/s3p+pYBV8KQas8/Lu2yumlqt2DcA5QD1b UHrhE3qEzB1v4KEUW73cboVbofBLXhHVz77RSHWxpGACaAjjzd/jlFjod X+fRQ/LAE6lMHgR7u8tdxA+m1X00EGBb8as7smgUMhpzd+g4uJTQIUvbq A==; X-CSE-ConnectionGUID: l0eaKsoaQFWWE6NXbuA4ew== X-CSE-MsgGUID: kKk1YBw1Rhy5wKvr3BeFwQ== X-IronPort-AV: E=McAfee;i="6800,10657,11662"; a="72860692" X-IronPort-AV: E=Sophos;i="6.21,203,1763452800"; d="scan'208";a="72860692" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jan 2026 09:19:08 -0800 X-CSE-ConnectionGUID: /aNk4qLyQMyUYi1IWqy4gg== X-CSE-MsgGUID: mCsnABl+Qw+vMofeJ94WGg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,203,1763452800"; d="scan'208";a="206992514" Received: from sghuge-mobl2.amr.corp.intel.com (HELO [10.125.109.25]) ([10.125.109.25]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jan 2026 09:19:07 -0800 Message-ID: <7cbac499-6145-4b83-873c-c2d283f9cb79@intel.com> Date: Mon, 5 Jan 2026 09:19:07 -0800 Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 0/3] Expose TDX Module version To: Kiryl Shutsemau Cc: Chao Gao , kvm@vger.kernel.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, x86@kernel.org, vishal.l.verma@intel.com, kai.huang@intel.com, dan.j.williams@intel.com, yilun.xu@linux.intel.com, vannapurve@google.com, Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Ingo Molnar , Rick Edgecombe , Thomas Gleixner References: <20260105074350.98564-1-chao.gao@intel.com> From: Dave Hansen Content-Language: en-US Autocrypt: addr=dave.hansen@intel.com; keydata= xsFNBE6HMP0BEADIMA3XYkQfF3dwHlj58Yjsc4E5y5G67cfbt8dvaUq2fx1lR0K9h1bOI6fC oAiUXvGAOxPDsB/P6UEOISPpLl5IuYsSwAeZGkdQ5g6m1xq7AlDJQZddhr/1DC/nMVa/2BoY 2UnKuZuSBu7lgOE193+7Uks3416N2hTkyKUSNkduyoZ9F5twiBhxPJwPtn/wnch6n5RsoXsb ygOEDxLEsSk/7eyFycjE+btUtAWZtx+HseyaGfqkZK0Z9bT1lsaHecmB203xShwCPT49Blxz VOab8668QpaEOdLGhtvrVYVK7x4skyT3nGWcgDCl5/Vp3TWA4K+IofwvXzX2ON/Mj7aQwf5W iC+3nWC7q0uxKwwsddJ0Nu+dpA/UORQWa1NiAftEoSpk5+nUUi0WE+5DRm0H+TXKBWMGNCFn c6+EKg5zQaa8KqymHcOrSXNPmzJuXvDQ8uj2J8XuzCZfK4uy1+YdIr0yyEMI7mdh4KX50LO1 pmowEqDh7dLShTOif/7UtQYrzYq9cPnjU2ZW4qd5Qz2joSGTG9eCXLz5PRe5SqHxv6ljk8mb ApNuY7bOXO/A7T2j5RwXIlcmssqIjBcxsRRoIbpCwWWGjkYjzYCjgsNFL6rt4OL11OUF37wL QcTl7fbCGv53KfKPdYD5hcbguLKi/aCccJK18ZwNjFhqr4MliQARAQABzUVEYXZpZCBDaHJp c3RvcGhlciBIYW5zZW4gKEludGVsIFdvcmsgQWRkcmVzcykgPGRhdmUuaGFuc2VuQGludGVs LmNvbT7CwXgEEwECACIFAlQ+9J0CGwMGCwkIBwMCBhUIAgkKCwQWAgMBAh4BAheAAAoJEGg1 lTBwyZKwLZUP/0dnbhDc229u2u6WtK1s1cSd9WsflGXGagkR6liJ4um3XCfYWDHvIdkHYC1t MNcVHFBwmQkawxsYvgO8kXT3SaFZe4ISfB4K4CL2qp4JO+nJdlFUbZI7cz/Td9z8nHjMcWYF IQuTsWOLs/LBMTs+ANumibtw6UkiGVD3dfHJAOPNApjVr+M0P/lVmTeP8w0uVcd2syiaU5jB aht9CYATn+ytFGWZnBEEQFnqcibIaOrmoBLu2b3fKJEd8Jp7NHDSIdrvrMjYynmc6sZKUqH2 I1qOevaa8jUg7wlLJAWGfIqnu85kkqrVOkbNbk4TPub7VOqA6qG5GCNEIv6ZY7HLYd/vAkVY E8Plzq/NwLAuOWxvGrOl7OPuwVeR4hBDfcrNb990MFPpjGgACzAZyjdmYoMu8j3/MAEW4P0z F5+EYJAOZ+z212y1pchNNauehORXgjrNKsZwxwKpPY9qb84E3O9KYpwfATsqOoQ6tTgr+1BR CCwP712H+E9U5HJ0iibN/CDZFVPL1bRerHziuwuQuvE0qWg0+0SChFe9oq0KAwEkVs6ZDMB2 P16MieEEQ6StQRlvy2YBv80L1TMl3T90Bo1UUn6ARXEpcbFE0/aORH/jEXcRteb+vuik5UGY 5TsyLYdPur3TXm7XDBdmmyQVJjnJKYK9AQxj95KlXLVO38lczsFNBFRjzmoBEACyAxbvUEhd GDGNg0JhDdezyTdN8C9BFsdxyTLnSH31NRiyp1QtuxvcqGZjb2trDVuCbIzRrgMZLVgo3upr MIOx1CXEgmn23Zhh0EpdVHM8IKx9Z7V0r+rrpRWFE8/wQZngKYVi49PGoZj50ZEifEJ5qn/H Nsp2+Y+bTUjDdgWMATg9DiFMyv8fvoqgNsNyrrZTnSgoLzdxr89FGHZCoSoAK8gfgFHuO54B lI8QOfPDG9WDPJ66HCodjTlBEr/Cwq6GruxS5i2Y33YVqxvFvDa1tUtl+iJ2SWKS9kCai2DR 3BwVONJEYSDQaven/EHMlY1q8Vln3lGPsS11vSUK3QcNJjmrgYxH5KsVsf6PNRj9mp8Z1kIG qjRx08+nnyStWC0gZH6NrYyS9rpqH3j+hA2WcI7De51L4Rv9pFwzp161mvtc6eC/GxaiUGuH BNAVP0PY0fqvIC68p3rLIAW3f97uv4ce2RSQ7LbsPsimOeCo/5vgS6YQsj83E+AipPr09Caj 0hloj+hFoqiticNpmsxdWKoOsV0PftcQvBCCYuhKbZV9s5hjt9qn8CE86A5g5KqDf83Fxqm/ vXKgHNFHE5zgXGZnrmaf6resQzbvJHO0Fb0CcIohzrpPaL3YepcLDoCCgElGMGQjdCcSQ+Ci FCRl0Bvyj1YZUql+ZkptgGjikQARAQABwsFfBBgBAgAJBQJUY85qAhsMAAoJEGg1lTBwyZKw l4IQAIKHs/9po4spZDFyfDjunimEhVHqlUt7ggR1Hsl/tkvTSze8pI1P6dGp2XW6AnH1iayn yRcoyT0ZJ+Zmm4xAH1zqKjWplzqdb/dO28qk0bPso8+1oPO8oDhLm1+tY+cOvufXkBTm+whm +AyNTjaCRt6aSMnA/QHVGSJ8grrTJCoACVNhnXg/R0g90g8iV8Q+IBZyDkG0tBThaDdw1B2l asInUTeb9EiVfL/Zjdg5VWiF9LL7iS+9hTeVdR09vThQ/DhVbCNxVk+DtyBHsjOKifrVsYep WpRGBIAu3bK8eXtyvrw1igWTNs2wazJ71+0z2jMzbclKAyRHKU9JdN6Hkkgr2nPb561yjcB8 sIq1pFXKyO+nKy6SZYxOvHxCcjk2fkw6UmPU6/j/nQlj2lfOAgNVKuDLothIxzi8pndB8Jju KktE5HJqUUMXePkAYIxEQ0mMc8Po7tuXdejgPMwgP7x65xtfEqI0RuzbUioFltsp1jUaRwQZ MTsCeQDdjpgHsj+P2ZDeEKCbma4m6Ez/YWs4+zDm1X8uZDkZcfQlD9NldbKDJEXLIjYWo1PH hYepSffIWPyvBMBTW2W5FRjJ4vLRrJSUoEfJuPQ3vW9Y73foyo/qFoURHO48AinGPZ7PC7TF vUaNOTjKedrqHkaOcqB185ahG2had0xnFsDPlx5y In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 1/5/26 09:04, Kiryl Shutsemau wrote: >> What are other CPU vendors doing for this? SEV? CCA? S390? How are their >> firmware versions exposed? What about other things in the Intel world >> like CPU microcode or the billion other chunks of firmware? How about >> hypervisors? Do they expose their versions to guests with an explicit >> ABI? Are those exposed to userspace? > My first thought was that it should be under /sys/hypervisor/, no? > > So far hypervisor_kobj only used by Xen and S390. As with everything else around TDX, it's not clear to me. The TDX module is a new middle ground between the hypervisor and CPU. It's literally there to arbitrate between the trusted CPU world and the untrusted hypervisor world. It's messy because there was (previously) no component there. It's new space. We could (theoretically) a Linux guest running under Xen the hypervisor using TDX. So we can't trivially just take over /sys/hypervisor for TDX. It's equally valid to sit here and claim that the TDX module is CPU microcode. Sure, there's source code for it, but only Intel can bless it, a version of it is loaded by the BIOS and can be updated by the OS. It's not _super_ different conceptually than SGX XuCode. The main thing that makes the TDX module _not_ CPU microcode is that it's managed completely separately and there's almost no connection between this: /sys/devices/system/cpu/cpu*/microcode/version and the TDX module version. Since there's a dearth of discussion of this topic in the changelog or cover letter, my working assumption is that Chao did not consider any of this before posting.