From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B5798211291 for ; Thu, 12 Dec 2024 10:54:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.17 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734000854; cv=none; b=m0+8LhcWKHcFPWBhq4n2kqg1ofcA1JO3Xe8Jk2J5KMfG3b8Zf7FiqTPUtG5ZIWahVlt+FUyrkxJX335VZZRcavAFHGKjwug8umeOaoYmAjHGpW8kwzKydARmD5L1n64fJr8ddK6g1CooEWWehc+ej6AZx8o1NyWSQ9mV+QPTZ/M= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734000854; c=relaxed/simple; bh=MOlQQdO5lK3U572ldkpTBbrDmAKTbjY10M2pA09lNNg=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=J7al9qFCaJVLWdmJfka1FOfwbFNQFkO1+G7zqMYME+OnX3gt5oLqhFgtLCdP/qk5poSbgxMfc2iMjTkgOXJjo9/w5MuqyOkv5yrNEHAQWzQNWVBoDDOU5rripy4FrJSj4AB/ds0UuM6ELdxXMgKAlzuRuTVNXUEihoMjIZ13hjk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=XpXBYVMj; arc=none smtp.client-ip=198.175.65.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="XpXBYVMj" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734000853; x=1765536853; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=MOlQQdO5lK3U572ldkpTBbrDmAKTbjY10M2pA09lNNg=; b=XpXBYVMjMwI7u/Ep1QMtoVP4hiTzpydLKJq0fEB0oOx2o6hQTH9xyZF8 /ZFWYh+HPK7AhO/Upqx4SHf43netBAacNOb/4AHTXd0zV4EDcplknXs1f a6qRYtCozzl6hpDqohzlKl8joiOtuhPB/hcZzzJROX+9S4HKftGSlotBs itTpevrbWTgSWcKMf6wTnAQTbICCGPZFqv+I4quFLSl2qnEVwbju67AxA xsylh7LuYIjyEOjaEfAPQeMJ+boOhCiu3+3vJGCqDFPj4nqgPonzwC/Ex gx0cxxzqElkinSxkTdZh+F6uH73nTaP1xd/N6wUZtZG1zKXIc9EfqmYJy A==; X-CSE-ConnectionGUID: TzU6Tev5Tbm1T0LhwYlfag== X-CSE-MsgGUID: OznFBOQkTs6QoSVJmwxTWg== X-IronPort-AV: E=McAfee;i="6700,10204,11283"; a="34457136" X-IronPort-AV: E=Sophos;i="6.12,228,1728975600"; d="scan'208";a="34457136" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Dec 2024 02:54:12 -0800 X-CSE-ConnectionGUID: tQTjDtP0TNeQQ72BIFVR6A== X-CSE-MsgGUID: DEbwxkEuR0ObeawGhvzQ+Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="119439918" Received: from yilunxu-optiplex-7050.sh.intel.com (HELO localhost) ([10.239.159.165]) by fmviesa002.fm.intel.com with ESMTP; 12 Dec 2024 02:54:10 -0800 Date: Thu, 12 Dec 2024 18:50:52 +0800 From: Xu Yilun To: Dan Williams Cc: linux-coco@lists.linux.dev, Bjorn Helgaas , Lukas Wunner , Samuel Ortiz , Alexey Kardashevskiy , linux-pci@vger.kernel.org, gregkh@linuxfoundation.org Subject: Re: [PATCH 08/11] PCI/IDE: Add IDE establishment helpers Message-ID: References: <173343739517.1074769.13134786548545925484.stgit@dwillia2-xfh.jf.intel.com> <173343744264.1074769.10935494914881159519.stgit@dwillia2-xfh.jf.intel.com> Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <173343744264.1074769.10935494914881159519.stgit@dwillia2-xfh.jf.intel.com> > +static void __pci_ide_stream_setup(struct pci_dev *pdev, struct pci_ide *ide) > +{ > + int pos; > + u32 val; > + > + pos = sel_ide_offset(pdev->sel_ide_cap, ide->stream_id, > + pdev->nr_ide_mem); > + > + val = FIELD_PREP(PCI_IDE_SEL_RID_1_LIMIT_MASK, ide->devid_end); > + pci_write_config_dword(pdev, pos + PCI_IDE_SEL_RID_1, val); > + > + val = FIELD_PREP(PCI_IDE_SEL_RID_2_VALID, 1) | > + FIELD_PREP(PCI_IDE_SEL_RID_2_BASE_MASK, ide->devid_start) | > + FIELD_PREP(PCI_IDE_SEL_RID_2_SEG_MASK, ide->domain); > + pci_write_config_dword(pdev, pos + PCI_IDE_SEL_RID_2, val); > + > + for (int i = 0; i < ide->nr_mem; i++) { > + val = FIELD_PREP(PCI_IDE_SEL_ADDR_1_VALID, 1) | > + FIELD_PREP(PCI_IDE_SEL_ADDR_1_BASE_LOW_MASK, > + lower_32_bits(ide->mem[i].start) >> > + PCI_IDE_SEL_ADDR_1_BASE_LOW_SHIFT) | > + FIELD_PREP(PCI_IDE_SEL_ADDR_1_LIMIT_LOW_MASK, > + lower_32_bits(ide->mem[i].end) >> > + PCI_IDE_SEL_ADDR_1_LIMIT_LOW_SHIFT); Oh, I missunderstood the _LOW_SHIFT Macros. But still think if they could be moved out of pci_reg.h. Placing in pci_reg.h makes me think they are some register field offsets. Thanks, Yilun