From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D2A714532C; Mon, 10 Jun 2024 17:27:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718040448; cv=none; b=YLx63nASStJKPVcJViCOegmaPVF4pAwT2u2TFhbMhes0WSbDHSpHgdfbu3JA5aNhwpCRLH8/gts7y0+LtunVipgSEiEUYhZN5Qt7zTWplqG3M8TvgzLoSwe0oa92uTU82r4gxTL11XEFuDQb7lawpAFQcthb7g29HuY4Dxr8BKg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718040448; c=relaxed/simple; bh=wJYRldg3T8FDmjjLK/CGxgQ4cydiTmDEgBrsTZOAVPA=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=FKl2WC3imrOGQG/+VEJFOgUNF9GO/zU93mXDN8n7MhMsCcWX4aS0UBLxnuyQIb4tkqiMgunLzsgv7DX6q3T+81hpXzHbFjSUnA3knIWTsUhwHObrjVNjE49VLZMiF6iqTiwS+CqWL1eA2/iAdbLxB1ovgnrBWO6hcUK6yuPQV3U= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id A4E42C4AF1C; Mon, 10 Jun 2024 17:27:24 +0000 (UTC) Date: Mon, 10 Jun 2024 18:27:22 +0100 From: Catalin Marinas To: Steven Price Cc: kvm@vger.kernel.org, kvmarm@lists.linux.dev, Suzuki K Poulose , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni Subject: Re: [PATCH v3 09/14] arm64: Enable memory encrypt for Realms Message-ID: References: <20240605093006.145492-1-steven.price@arm.com> <20240605093006.145492-10-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240605093006.145492-10-steven.price@arm.com> On Wed, Jun 05, 2024 at 10:30:01AM +0100, Steven Price wrote: > +static int __set_memory_encrypted(unsigned long addr, > + int numpages, > + bool encrypt) > +{ > + unsigned long set_prot = 0, clear_prot = 0; > + phys_addr_t start, end; > + int ret; > + > + if (!is_realm_world()) > + return 0; > + > + if (!__is_lm_address(addr)) > + return -EINVAL; > + > + start = __virt_to_phys(addr); > + end = start + numpages * PAGE_SIZE; > + > + /* > + * Break the mapping before we make any changes to avoid stale TLB > + * entries or Synchronous External Aborts caused by RIPAS_EMPTY > + */ > + ret = __change_memory_common(addr, PAGE_SIZE * numpages, > + __pgprot(0), > + __pgprot(PTE_VALID)); > + > + if (encrypt) { > + clear_prot = PROT_NS_SHARED; > + ret = rsi_set_memory_range_protected(start, end); > + } else { > + set_prot = PROT_NS_SHARED; > + ret = rsi_set_memory_range_shared(start, end); > + } > + > + if (ret) > + return ret; > + > + set_prot |= PTE_VALID; > + > + return __change_memory_common(addr, PAGE_SIZE * numpages, > + __pgprot(set_prot), > + __pgprot(clear_prot)); > +} This works, does break-before-make and also rejects vmalloc() ranges (for the time being). One particular aspect I don't like is doing the TLBI twice. It's sufficient to do it when you first make the pte invalid. We could guess this in __change_memory_common() if set_mask has PTE_VALID. The call sites are restricted to this file, just add a comment. An alternative would be to add a bool flush argument to this function. -- Catalin