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AFNElJ8g/xKfgakRjrh9flrGbJIRftbhorOhRmSA7pb++LcMhr8+8XA0tthxeDif/dAUu+n5insAWKohbcLe@lists.linux.dev X-Gm-Message-State: AOJu0YwelNZB4ZQ3VibtJI2Kq6m7xliSsp2vUyel70DuTeGEiTvIo7ON 3drOYW9lIt0JEqn3A/evOzzlnSCX5o5nLasTr1kpMFaEmTpdNEYUv+c4WKKGSElHWOS3BzhLnYW 2jTu8+A== X-Received: from pfj1.prod.google.com ([2002:a05:6a00:a401:b0:82f:2a0d:b24c]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a00:90a9:b0:834:e605:9927 with SMTP id d2e1a72fcca58-834fdcb93b7mr4649065b3a.37.1777576825076; Thu, 30 Apr 2026 12:20:25 -0700 (PDT) Date: Thu, 30 Apr 2026 12:20:23 -0700 In-Reply-To: <231efd4e9267d3dbb8c63e57b3a43567c965e24a.camel@intel.com> Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260430014852.24183-1-yan.y.zhao@intel.com> <20260430014948.24226-1-yan.y.zhao@intel.com> <231efd4e9267d3dbb8c63e57b3a43567c965e24a.camel@intel.com> Message-ID: Subject: Re: [PATCH v2 2/4] x86/tdx: Use PFN directly for unmapping guest private memory From: Sean Christopherson To: Rick P Edgecombe Cc: Ackerley Tng , "pbonzini@redhat.com" , Yan Y Zhao , "dave.hansen@linux.intel.com" , Sagi Shahar , Isaku Yamahata , "x86@kernel.org" , "kas@kernel.org" , "yilun.xu@linux.intel.com" , "bp@alien8.de" , "mingo@redhat.com" , "linux-kernel@vger.kernel.org" , Kai Huang , "kvm@vger.kernel.org" , "linux-coco@lists.linux.dev" , Xiaoyao Li , "tglx@kernel.org" , "binbin.wu@linux.intel.com" , Vishal Annapurve Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On Thu, Apr 30, 2026, Rick P Edgecombe wrote: > On Thu, 2026-04-30 at 11:17 -0700, Ackerley Tng wrote: > > > =C2=A0 { > > > =C2=A0=C2=A0 const void *zero_page =3D (const void *)page_address(ZER= O_PAGE(0)); > > > =C2=A0=C2=A0 unsigned long phys, end; > > > @@ -729,6 +729,7 @@ static void tdx_quirk_reset_paddr(unsigned long b= ase, unsigned long size) > > > =C2=A0=C2=A0 */ > > > =C2=A0=C2=A0 mb(); > > > =C2=A0 } > > > +EXPORT_SYMBOL_FOR_KVM(tdx_quirk_reset_paddr); > > >=20 > > > =C2=A0 void tdx_quirk_reset_page(struct page *page) > > > =C2=A0 { > > > @@ -1920,17 +1921,17 @@ u64 tdh_phymem_page_wbinvd_tdr(struct tdx_td = *td) > > > =C2=A0 { > > > =C2=A0=C2=A0 struct tdx_module_args args =3D {}; > > >=20 > > > - args.rcx =3D mk_keyed_paddr(tdx_global_keyid, td->tdr_page); > > > + args.rcx =3D mk_keyed_paddr(tdx_global_keyid, page_to_pfn(td->tdr_p= age)); > >=20 > > Should mk_keyed_paddr() be updated to have a return type of phys_addr_t= ? > > I guess in this case since mk_keyed_paddr() is pretty much an internal > > function, returning u64 also makes sense to indicate that it should onl= y > > be used to set 64 bit registers. >=20 > Yea, this is used to construct u64 inputs for seamcall args. So I think i= t > should keep returning u64s. +1. IMO, we should treat the TDX-Module as an extension of hardware and pa= ss in u64s where the spec says it takes a 64-bit value.