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AFNElJ8mb9AnV8t7H2jbsDt2qyN+N7QcJAAVHzVlXhVcD3PlTe5dJW7w48zQCr5yjGbhIXYTNBI9wxYkVqov@lists.linux.dev X-Gm-Message-State: AOJu0YybDdrU7Jyx3aVhUSGrqavgVU597LN7hY2Bn10oz0d7wIhu0uxq wg3rK3u9D59FKYRNRu9RNsx9FXlIoE28hFE8WSFX1tY/Z31rc9Zw6gP6tYx4b2eGVR2+RJr2FJN 5RbJ0lA== X-Received: from pfbg7.prod.google.com ([2002:a05:6a00:ae07:b0:837:c09c:9cce]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a00:2793:b0:83e:26b:528c with SMTP id d2e1a72fcca58-83f33d26f67mr16065245b3a.28.1779137470943; Mon, 18 May 2026 13:51:10 -0700 (PDT) Date: Mon, 18 May 2026 13:51:10 -0700 In-Reply-To: <136d277dba2ac681ed7607a436f55e2fd1975ec5.camel@intel.com> Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260514215355.1648463-1-seanjc@google.com> <20260514215355.1648463-9-seanjc@google.com> <136d277dba2ac681ed7607a436f55e2fd1975ec5.camel@intel.com> Message-ID: Subject: Re: [PATCH v2 08/15] KVM: x86: Add mode-aware versions of kvm__{read,write}() helpers From: Sean Christopherson To: Kai Huang Cc: "pbonzini@redhat.com" , "kas@kernel.org" , "vkuznets@redhat.com" , "dwmw2@infradead.org" , "paul@xen.org" , Rick P Edgecombe , "x86@kernel.org" , "binbin.wu@linux.intel.com" , "dave.hansen@linux.intel.com" , "linux-kernel@vger.kernel.org" , "yosry@kernel.org" , "kvm@vger.kernel.org" , "linux-coco@lists.linux.dev" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On Mon, May 18, 2026, Kai Huang wrote: >=20 > > @@ -10413,29 +10413,30 @@ static int complete_hypercall_exit(struct kvm= _vcpu *vcpu) > > =C2=A0 > > =C2=A0 if (!is_64_bit_hypercall(vcpu)) > > =C2=A0 ret =3D (u32)ret; > > - kvm_rax_write(vcpu, ret); > > + kvm_rax_write_raw(vcpu, ret); > > =C2=A0 return kvm_skip_emulated_instruction(vcpu); > > =C2=A0} > >=20 >=20 > Nit: AFAICT if we use kvm_rax_write(vcpu, ret) instead of the "raw" vers= ion > here, we can then remove the >=20 > if (!is_64_bit_hypercall(vcpu)) > ret =3D (u32)ret; No, because sneakily, is_64_bit_hypercall() !=3D is_64_bit_mode(vcpu). And= because we also need to avoid calling is_64_bit_mode(). If we use kvm_rax_write(),= then the unpacked code will be: WARN_ON_ONCE(vcpu->arch.guest_state_protected); if (is_long_mode(vcpu)) kvm_x86_call(get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); else cs_l =3D 0; if (cs_l) vcpu->arch.regs[VCPU_REGS_RAX] =3D ret; else=09 vcpu->arch.regs[VCPU_REGS_RAX] =3D (u32)ret; whereas the (correct) behavior here is: if (vcpu->arch.guest_state_protected) cs_l =3D 1; else if (is_long_mode(vcpu)) kvm_x86_call(get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); else cs_l =3D 0; if (cs_l) vcpu->arch.regs[VCPU_REGS_RAX] =3D ret; else=09 vcpu->arch.regs[VCPU_REGS_RAX] =3D (u32)ret; I.e. using the non-raw version will trigger the WARN_ON_ONCE(), and will in= correctly truncate "ret" whenever cs_l is stale (which might be always?).