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X-CSE-ConnectionGUID: bhqY4lQCQEWCRM4TiSbPIg== X-CSE-MsgGUID: lHQuURPtTIiAq1O20KLxiw== X-IronPort-AV: E=McAfee;i="6800,10657,11685"; a="81154858" X-IronPort-AV: E=Sophos;i="6.21,258,1763452800"; d="scan'208";a="81154858" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2026 09:01:37 -0800 X-CSE-ConnectionGUID: wyBXLrvVQj2xUamy6Hfb1w== X-CSE-MsgGUID: cHTY54a6R8GQ3a4aSqdHyg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,258,1763452800"; d="scan'208";a="208393452" Received: from kcaccard-desk.amr.corp.intel.com (HELO [10.125.109.190]) ([10.125.109.190]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2026 09:01:36 -0800 Message-ID: Date: Wed, 28 Jan 2026 09:01:35 -0800 Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 05/26] coco/tdx-host: Expose TDX Module version To: Chao Gao , linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, x86@kernel.org Cc: reinette.chatre@intel.com, ira.weiny@intel.com, kai.huang@intel.com, dan.j.williams@intel.com, yilun.xu@linux.intel.com, sagis@google.com, vannapurve@google.com, paulmck@kernel.org, nik.borisov@suse.com, zhenzhong.duan@intel.com, seanjc@google.com, rick.p.edgecombe@intel.com, kas@kernel.org, dave.hansen@linux.intel.com, vishal.l.verma@intel.com References: <20260123145645.90444-1-chao.gao@intel.com> <20260123145645.90444-6-chao.gao@intel.com> From: Dave Hansen Content-Language: en-US Autocrypt: addr=dave.hansen@intel.com; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 1/23/26 06:55, Chao Gao wrote: ... > This approach follows the pattern used by microcode updates and > other CoCo implementations: > > 1. AMD has a PCI device for the PSP for SEV which provides an > existing place to hang their equivalent metadata. > > 2. ARM CCA will likely have a faux device (although it isn't obvious > if they have a need to export version information there) [1] > > 3. Microcode revisions are exposed as CPU device attributes I kinda disagree with the idea that this follows existing patterns. It uses a *NEW* pattern. AMD doesn't use a faux device because they *HAVE* a PCI device in their architecture. TDX doesn't have a PCI device in its hardware architecture. ARM CCA doesn't exist in the tree. CPU microcode doesn't use a faux device. For good reason. The microcode version is *actually* per-cpu. It can differ between CPU cores. The TDX module version is not per-cpu. There's one and only one global module. This is the reason that we need a global, unique device for TDX. I'm not saying that being new is a bad thing. But let's not pretend this is following any kind of existing pattern. Let's explain *why* it needs to be different.