From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5263623E35D; Mon, 7 Apr 2025 11:40:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744026045; cv=none; b=EqLPa82x9t2EdOYNeKHwmdXmJUwwzakSDYNT8J232Kr3pqr4gOCcs2mRchAMstW3cwkgBuxzBXsgntG3dxDU/eQhY/8QsXmL6MpLLHY6R9XbBUokY42g4USdfvwp6YFWlux64z+SbkPIDeRNfHDTt/66bEAFYGqHJCdETYuql54= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744026045; c=relaxed/simple; bh=vzyAKLHqu3gRIT3XigIACxVJDWJCCNJWkRCnR4vlrpU=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=iZRrNJQBAXLycI7EFiJyPDwDnDnbAXRvK2I/ah6YjlDh77Jml0hgKRFstpySu9aB+5gb2RyBoDGAYsGNs0jPsoj5AHda+HRt7F9IfXHSEknKbbIr3zPWtyVt6IOr5snXJvvlwKIQs8gVwYPANuAX5CF3tmh7XjduVrXEQL6eSek= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ihfvx7i3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ihfvx7i3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4031CC4CEDD; Mon, 7 Apr 2025 11:40:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744026044; bh=vzyAKLHqu3gRIT3XigIACxVJDWJCCNJWkRCnR4vlrpU=; h=From:To:Cc:Subject:In-Reply-To:References:Date:From; b=ihfvx7i3hTmS/r04UM0uF1arK6LEBDn5fWytpW7+ZiJsnRDfmKLwJBtzh7PN1XNSI u+znc1IeLnyjRrgKMkjD94YLwDy+wtZLg1H+uqMpTGNke8HlUc2cDCa5sLVuT2YSQg g2RqmcKfRwUpKnWGiNhh9HBrxMujr3oxWEnU1xxJ3WN8RqoFq5oCjQ7Kz+AprXY7CM q9vc4EozkL2+taALxeW3EFGp4AdYg9TZ1OSfRLODymwNydsqrEAhbszSLVr6fWRChT X8u1VlbYEIbqkl82fa1NwmOLeASjXl7YSgiLzOUMPlbythNvreSWcHUrQFYnXsDe+m g9XQKpYvS2tig== X-Mailer: emacs 30.1 (via feedmail 11-beta-1 I) From: Aneesh Kumar K.V To: Jason Gunthorpe Cc: Alexey Kardashevskiy , x86@kernel.org, kvm@vger.kernel.org, linux-crypto@vger.kernel.org, linux-pci@vger.kernel.org, linux-arch@vger.kernel.org, Sean Christopherson , Paolo Bonzini , Tom Lendacky , Ashish Kalra , Joerg Roedel , Suravee Suthikulpanit , Robin Murphy , Kevin Tian , Bjorn Helgaas , Dan Williams , Christoph Hellwig , Nikunj A Dadhania , Michael Roth , Vasant Hegde , Joao Martins , Nicolin Chen , Lu Baolu , Steve Sistare , Lukas Wunner , Jonathan Cameron , Suzuki K Poulose , Dionna Glaze , Yi Liu , iommu@lists.linux.dev, linux-coco@lists.linux.dev, Zhi Wang , AXu Yilun Subject: Re: [RFC PATCH v2 14/22] iommufd: Add TIO calls In-Reply-To: <20250401160340.GK186258@ziepe.ca> References: <20250218111017.491719-1-aik@amd.com> <20250218111017.491719-15-aik@amd.com> <20250401160340.GK186258@ziepe.ca> Date: Mon, 07 Apr 2025 17:10:29 +0530 Message-ID: Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain Jason Gunthorpe writes: > On Fri, Mar 28, 2025 at 10:57:18AM +0530, Aneesh Kumar K.V wrote: >> > +int iommufd_vdevice_tsm_bind_ioctl(struct iommufd_ucmd *ucmd) >> > +{ >> > + struct iommu_vdevice_tsm_bind *cmd = ucmd->cmd; >> > + struct iommufd_viommu *viommu; >> > + struct iommufd_vdevice *vdev; >> > + struct iommufd_device *idev; >> > + struct tsm_tdi *tdi; >> > + int rc = 0; >> > + >> > + viommu = iommufd_get_viommu(ucmd, cmd->viommu_id); >> > + if (IS_ERR(viommu)) >> > + return PTR_ERR(viommu); >> > >> >> Would this require an IOMMU_HWPT_ALLOC_NEST_PARENT page table >> allocation? > > Probably. That flag is what forces a S2 page table. > >> How would this work in cases where there's no need to set up Stage 1 >> IOMMU tables? > > Either attach the raw HWPT of the IOMMU_HWPT_ALLOC_NEST_PARENT or: > >> Alternatively, should we allocate an IOMMU_HWPT_ALLOC_NEST_PARENT with a >> Stage 1 disabled translation config? (In the ARM case, this could mean >> marking STE entries as Stage 1 bypass and Stage 2 translate.) > > For arm you mean IOMMU_HWPT_DATA_ARM_SMMUV3.. But yes, this can work > too and is mandatory if you want the various viommu linked features to > work. > I was trying to prototype this using kvmtool and I have run into some issues. First i needed the below change for vIOMMU alloc to work modified drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -4405,6 +4405,8 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) reg = readl_relaxed(smmu->base + ARM_SMMU_IDR3); if (FIELD_GET(IDR3_RIL, reg)) smmu->features |= ARM_SMMU_FEAT_RANGE_INV; + if (FIELD_GET(IDR3_FWB, reg)) + smmu->features |= ARM_SMMU_FEAT_S2FWB; /* IDR5 */ reg = readl_relaxed(smmu->base + ARM_SMMU_IDR5); Also current code don't allow a Stage 1 bypass, Stage2 translation when allocating HWPT. arm_vsmmu_alloc_domain_nested -> arm_smmu_validate_vste -> cfg = FIELD_GET(STRTAB_STE_0_CFG, le64_to_cpu(arg->ste[0])); if (cfg != STRTAB_STE_0_CFG_ABORT && cfg != STRTAB_STE_0_CFG_BYPASS && cfg != STRTAB_STE_0_CFG_S1_TRANS) return -EIO; This only allow a abort or bypass or stage1 translate/stage2 bypass config Also if we don't need stage1 table, what will iommufd_viommu_alloc_hwpt_nested() return? > >> Also, if a particular setup doesn't require creating IOMMU >> entries because the entire guest RAM is identity-mapped in the IOMMU, do >> we still need to make tsm_tdi_bind use this abstraction in iommufd? > > Even if the viommu will not be exposed to the guest I'm expecting that > iommufd will have a viommu object, just not use various features. We > are using viommu as the handle for the KVM, vmid and other things that > are likely important here. > > Jason -aneesh