From: "Stephan Müller" <smueller@chronox.de>
To: Herbert Xu <herbert@gondor.apana.org.au>
Cc: linux-crypto@vger.kernel.org
Subject: Re: Qualcomm QCE driver: XTS setkey only allows 128 bit AES
Date: Wed, 15 Feb 2017 08:28:25 +0100 [thread overview]
Message-ID: <1735310.xhZtslYW8T@positron.chronox.de> (raw)
In-Reply-To: <20170215040243.GA13703@gondor.apana.org.au>
Am Mittwoch, 15. Februar 2017, 12:02:43 CET schrieb Herbert Xu:
Hi Herbert,
> Stephan Müller <smueller@chronox.de> wrote:
> > Hi,
> >
> > The Qualcomm QCE driver implementation defines:
> > .flags = QCE_ALG_AES | QCE_MODE_XTS,
> > .name = "xts(aes)",
> > .drv_name = "xts-aes-qce",
> > .blocksize = AES_BLOCK_SIZE,
> > .ivsize = AES_BLOCK_SIZE,
> > .min_keysize = AES_MIN_KEY_SIZE,
> > .max_keysize = AES_MAX_KEY_SIZE,
> >
> > and
> >
> > alg->cra_ablkcipher.min_keysize = def->min_keysize;
> > alg->cra_ablkcipher.max_keysize = def->max_keysize;
> > alg->cra_ablkcipher.setkey = qce_ablkcipher_setkey;
> >
> > Thus, this driver has the limits of 128 to 256 bits for the key.
> > Furthermore, the common setkey function is used.
> >
> > May I ask how the key for AES XTS is supposed to be handled here
> > considering that the kernel crypto API expects that the AES key and the
> > tweak key is set via one setkey call. I.e. the setkey should expect 256
> > through 512 bits.
> If the hardware doesn't support it then it needs to be handled with
> a fallback. Shouldn't testmgr catch this though?
It should be caught there because there are test vectors with a klen of 64
bytes. Thus, the setkey should fail.
Ciao
Stephan
prev parent reply other threads:[~2017-02-15 7:28 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-13 15:30 Qualcomm QCE driver: XTS setkey only allows 128 bit AES Stephan Müller
2017-02-15 4:02 ` Herbert Xu
2017-02-15 7:28 ` Stephan Müller [this message]
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