From: David Miller <davem@davemloft.net>
To: herbert@gondor.apana.org.au
Cc: sparclinux@vger.kernel.org, linux-crypto@vger.kernel.org
Subject: Re: [PATCH] sparc64: Add CRC32C driver making use of the new crc32c opcode.
Date: Thu, 23 Aug 2012 09:20:43 -0700 (PDT) [thread overview]
Message-ID: <20120823.092043.1156875617277157051.davem@davemloft.net> (raw)
In-Reply-To: <20120823083654.GA13395@gondor.apana.org.au>
From: Herbert Xu <herbert@gondor.apana.org.au>
Date: Thu, 23 Aug 2012 16:36:54 +0800
> On Wed, Aug 22, 2012 at 08:52:31PM -0700, David Miller wrote:
>>
>> Signed-off-by: David S. Miller <davem@davemloft.net>
>
> Looks good to me.
Thanks for reviewing.
>> This was largely straightforward, except for two things.
>>
>> 1) The tests assume that the 32-bit crc is stored in the context in
>> cpu endian. The sparc64 crc32c opcode wants to work with a little
>> endian mode, but sparc64 is big-endian.
>
> We can still change this as nothing outside the kernel relies
> on the format of the context. For the time being all that's
> required is that it be identical between software and hardware
> implementations.
Ok, let's just leave it alone for now :-)
prev parent reply other threads:[~2012-08-23 16:20 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-08-22 9:21 [PATCH] sparc64: Add AES driver making use of the new aes opcodes David Miller
2012-08-22 13:40 ` Herbert Xu
2012-08-22 21:31 ` David Miller
2012-08-23 3:52 ` [PATCH] sparc64: Add CRC32C driver making use of the new crc32c opcode David Miller
2012-08-23 8:36 ` Herbert Xu
2012-08-23 16:20 ` David Miller [this message]
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