From: Ard Biesheuvel <ardb@kernel.org>
To: linux-crypto@vger.kernel.org
Cc: herbert@gondor.apana.org.au, Ard Biesheuvel <ardb@kernel.org>,
Nick Desaulniers <ndesaulniers@google.com>,
Stefan Agner <stefan@agner.ch>, Peter Smith <Peter.Smith@arm.com>
Subject: [PATCH v2 1/2] crypto: arm/sha256-neon - avoid ADRL pseudo instruction
Date: Wed, 16 Sep 2020 09:14:17 +0300 [thread overview]
Message-ID: <20200916061418.9197-2-ardb@kernel.org> (raw)
In-Reply-To: <20200916061418.9197-1-ardb@kernel.org>
The ADRL pseudo instruction is not an architectural construct, but a
convenience macro that was supported by the ARM proprietary assembler
and adopted by binutils GAS as well, but only when assembling in 32-bit
ARM mode. Therefore, it can only be used in assembler code that is known
to assemble in ARM mode only, but as it turns out, the Clang assembler
does not implement ADRL at all, and so it is better to get rid of it
entirely.
So replace the ADRL instruction with a ADR instruction that refers to
a nearer symbol, and apply the delta explicitly using an additional
instruction.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
---
arch/arm/crypto/sha256-armv4.pl | 4 ++--
arch/arm/crypto/sha256-core.S_shipped | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/crypto/sha256-armv4.pl b/arch/arm/crypto/sha256-armv4.pl
index 9f96ff48e4a8..f3a2b54efd4e 100644
--- a/arch/arm/crypto/sha256-armv4.pl
+++ b/arch/arm/crypto/sha256-armv4.pl
@@ -175,7 +175,6 @@ $code=<<___;
#else
.syntax unified
# ifdef __thumb2__
-# define adrl adr
.thumb
# else
.code 32
@@ -471,7 +470,8 @@ sha256_block_data_order_neon:
stmdb sp!,{r4-r12,lr}
sub $H,sp,#16*4+16
- adrl $Ktbl,K256
+ adr $Ktbl,.Lsha256_block_data_order
+ sub $Ktbl,$Ktbl,#.Lsha256_block_data_order-K256
bic $H,$H,#15 @ align for 128-bit stores
mov $t2,sp
mov sp,$H @ alloca
diff --git a/arch/arm/crypto/sha256-core.S_shipped b/arch/arm/crypto/sha256-core.S_shipped
index ea04b2ab0c33..6363014a50d7 100644
--- a/arch/arm/crypto/sha256-core.S_shipped
+++ b/arch/arm/crypto/sha256-core.S_shipped
@@ -56,7 +56,6 @@
#else
.syntax unified
# ifdef __thumb2__
-# define adrl adr
.thumb
# else
.code 32
@@ -1885,7 +1884,8 @@ sha256_block_data_order_neon:
stmdb sp!,{r4-r12,lr}
sub r11,sp,#16*4+16
- adrl r14,K256
+ adr r14,.Lsha256_block_data_order
+ sub r14,r14,#.Lsha256_block_data_order-K256
bic r11,r11,#15 @ align for 128-bit stores
mov r12,sp
mov sp,r11 @ alloca
--
2.17.1
next prev parent reply other threads:[~2020-09-16 6:14 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-16 6:14 [PATCH v2 0/2] crypto: arm/sha-neon - avoid ADRL instructions Ard Biesheuvel
2020-09-16 6:14 ` Ard Biesheuvel [this message]
2020-09-16 6:14 ` [PATCH v2 2/2] crypto: arm/sha512-neon - avoid ADRL pseudo instruction Ard Biesheuvel
2020-09-17 0:53 ` [PATCH v2 0/2] crypto: arm/sha-neon - avoid ADRL instructions Nick Desaulniers
2020-09-17 6:08 ` Ard Biesheuvel
2020-09-18 20:08 ` Nick Desaulniers
2020-09-18 20:30 ` Ard Biesheuvel
2020-09-25 8:11 ` Herbert Xu
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