Re: [PATCH v4 04/12] RISC-V: add vector crypto extension detection

Eric Biggers
2023-07-21T05:49:27Z

On Tue, Jul 11, 2023 at 05:37:35PM +0200, Heiko Stuebner wrote:
> From: Heiko Stuebner <heiko.stuebner@vrull.eu>
>
> Add detection for some extensions of the vector-crypto specification:
> - Zvkb: Vector Bit-manipulation used in Cryptography
> - Zvkg: Vector GCM/GMAC
> - Zvknha and Zvknhb: NIST Algorithm Suite
> - Zvkns: AES-128, AES-256 Single Round Suite
> - Zvksed: ShangMi Algorithm Suite
> - Zvksh: ShangMi Algorithm Suite
>
> As their use is very specific and will likely be limited to special places
> we expect current code to just pre-encode those instructions, so right now
> we don't introduce toolchain requirements.
>
> Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
> ---
> arch/riscv/include/asm/hwcap.h | 9 ++++++
> arch/riscv/kernel/cpu.c | 8 ++++++
> arch/riscv/kernel/cpufeature.c | 50 ++++++++++++++++++++++++++++++++++
> 3 files changed, 67 insertions(+)
>
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index b80ca6e77088..0f5172fa87b0 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -64,6 +64,15 @@
> #define RISCV_ISA_EXT_ZKSED 51
> #define RISCV_ISA_EXT_ZKSH 52
> #define RISCV_ISA_EXT_ZKT 53
> +#define RISCV_ISA_EXT_ZVBB 54
> +#define RISCV_ISA_EXT_ZVBC 55
> +#define RISCV_ISA_EXT_ZVKG 56
> +#define RISCV_ISA_EXT_ZVKNED 57
> +#define RISCV_ISA_EXT_ZVKNHA 58
> +#define RISCV_ISA_EXT_ZVKNHB 59
> +#define RISCV_ISA_EXT_ZVKSED 60
> +#define RISCV_ISA_EXT_ZVKSH 61
> +#define RISCV_ISA_EXT_ZVKT 62

It would be helpful if each RISCV_ISA_EXT_* definition had a comment that spells
out what it stands for, similar to what arch/x86/include/asm/cpufeatures.h does.
I know they can all be looked up, and they're sort of mnemonic, but it would be
helpful.

- Eric