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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38c2a1764e9sm698524f8f.17.2025.01.23.12.58.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jan 2025 12:58:11 -0800 (PST) Date: Thu, 23 Jan 2025 20:58:10 +0000 From: David Laight To: "Theodore Ts'o" Cc: Eric Biggers , Linus Torvalds , linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, Ard Biesheuvel , Chao Yu , "Darrick J. Wong" , Geert Uytterhoeven , Kent Overstreet , "Martin K. Petersen" , Michael Ellerman , Vinicius Peixoto , WangYuli Subject: Re: [GIT PULL] CRC updates for 6.14 Message-ID: <20250123205810.744c8823@pumpkin> In-Reply-To: <20250123140744.GB3875121@mit.edu> References: <20250119225118.GA15398@sol.localdomain> <20250123051633.GA183612@sol.localdomain> <20250123074618.GB183612@sol.localdomain> <20250123140744.GB3875121@mit.edu> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Thu, 23 Jan 2025 09:07:44 -0500 "Theodore Ts'o" wrote: > On Wed, Jan 22, 2025 at 11:46:18PM -0800, Eric Biggers wrote: > > > > Actually, I'm tempted to just provide slice-by-1 (a.k.a. byte-by-byte) as the > > only generic CRC32 implementation. The generic code has become increasingly > > irrelevant due to the arch-optimized code existing. The arch-optimized code > > tends to be 10 to 100 times faster on long messages. > > Yeah, that's my intuition as well; I would think the CPU's that > don't have a CRC32 optimization instruction(s) would probably be the > most sensitive to dcache thrashing. > > But given that Geert ran into this on m68k (I assume), maybe we could > have him benchmark the various crc32 generic implementation to see if > we is the best for him? That is, assuming that he cares (which he > might not. :-). The difference between the clock speed and main memory speed on an m68k will be a lot less than on anything more recent. So I suspect the effect of cache misses is much less (or more likely it is pretty much always getting a cache miss). Brain wakes up, does the m68k even have a D-cache? Checks the m68k user manual section 6 - it only has a I-cache (64 32-bit words). So the important thing is probably keeping the loop small. A cpu board might have an external data cache. For a small memory footprint it might be worth considering 4 bits at a time. So a 16 word (64 byte) lookup table. Thinks.... You can xor a data byte onto the crc 'accumulator' and then do two separate table lookups for each of the high nibbles and xor both onto it before the rotate. That is probably a reasonable compromise. David