From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.166.228]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6D521F0E37; Tue, 13 May 2025 08:55:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.19.166.228 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747126537; cv=none; b=bN6f/IOQKRbeuD0srQZHZKVd8no7fGn66qbyNuy3LS86XNErqDghZ5+nLFFJ/BX4T1s64L9Q6eNR0z3/h8i2xW+GqFyuzXiS2vWMRbjVHqbxqfzBm//lRA6+SqWJZza6G1I+2m373OfNOy28Ygx7gFNau1jV5Tb81YBFS/JZESc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747126537; c=relaxed/simple; bh=F40AeLmeMX5m8olg6Vqf4yOMi3mKo1f5RUVrBVNGd+8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=NwVbAbxQIw3ugk1cnFB1LA8+JNoPa8Yxe4sf16WDogmC32YQYMFkJ765eGq0ZCeIyF4Vt1640ozeyikYyQ4lCPzJ/4djK1Hknq/Nd/VXhfrDxKanTq3PaMSxeQut05JuavppeepcIvJm0pjj7tu5isNbTD+907Spej9jpBnpBng= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=rvGWi/Ai; arc=none smtp.client-ip=192.19.166.228 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="rvGWi/Ai" Received: from mail-lvn-it-01.broadcom.com (mail-lvn-it-01.lvn.broadcom.net [10.36.132.253]) by relay.smtp-ext.broadcom.com (Postfix) with ESMTP id E2B23C0000F3; Tue, 13 May 2025 01:55:34 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com E2B23C0000F3 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1747126534; bh=F40AeLmeMX5m8olg6Vqf4yOMi3mKo1f5RUVrBVNGd+8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rvGWi/AiZvD052YcJ9UhR2UpBt8NiNPxyKQfs5RY8SA+gl4sMyOqbdKTJs8sg0bdH ALMqn5iM95rqXX7kluAz9VVArtQV4u3T1shJX0WOAxPx8hoyGQZfI0CaWRz/AjGk6D TwmfZiLsU9cANubq9LArMy/e90vImRWiWvkB05Sc= Received: from fainelli-desktop.igp.broadcom.net (fainelli-desktop.dhcp.broadcom.net [10.67.48.245]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail-lvn-it-01.broadcom.com (Postfix) with ESMTPSA id A900918000530; Tue, 13 May 2025 01:55:34 -0700 (PDT) From: Florian Fainelli To: bcm-kernel-feedback-list@broadcom.com, Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , William Zhang , Anand Gore , Kursad Oney , Florian Fainelli , =?iso-8859-2?q?Rafa=B3_Mi=B3ecki?= , Olivia Mackall , Ray Jui , Scott Branden Cc: Florian Fainelli , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-crypto@vger.kernel.org Subject: Re: [PATCH v3 04/12] ARM: dts: bcm6855: Add BCMBCA peripherals Date: Tue, 13 May 2025 01:55:34 -0700 Message-ID: <20250513085534.2043482-1-florian.fainelli@broadcom.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250512-bcmbca-peripherals-arm-v3-4-86f97ab4326f@linaro.org> References: <20250512-bcmbca-peripherals-arm-v3-0-86f97ab4326f@linaro.org> <20250512-bcmbca-peripherals-arm-v3-4-86f97ab4326f@linaro.org> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Florian Fainelli On Mon, 12 May 2025 14:05:50 +0200, Linus Walleij wrote: > All the BCMBCA SoCs share a set of peripherals at 0xff800000, > albeit at slightly varying memory locations on the bus and > with varying IRQ assignments. > > Add the first and second watchdog, GPIO, RNG, LED, DMA and > second PL011 UART blocks for the BCM6855 based on the vendor > files 6855_map_part.h and 6855_intr.h from the > "bcmopen-consumer" code drop. > > This SoC has up to 256 possible GPIOs due to having 8 > registers with 32 GPIOs in each available. > > Signed-off-by: Linus Walleij > --- Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks! -- Florian