Re: lib/crypto: riscv: crypto_zvkb crashes on selftest if no misaligned vector support

[Eric Biggers <ebiggers@kernel.org>]

On Sun, Nov 30, 2025 at 11:59:58AM +0100, Ard Biesheuvel wrote:
> On Sun, 30 Nov 2025 at 10:13, Vivian Wang <wangruikang@iscas.ac.cn> wrote:
> >
> > Hi,
> >
> > We ran into a problem with chacha_zvkb, where having:
> >
> > - OpenSBI 1.7+ (for FWFT support)
> > - CRYPTO_CHACHA20POLY1305=y and CRYPTO_SELFTESTS=y (and deps, of course)
> > - Hardware with Zvkb support
> > - Hardware *without* misaligned vector load/store support
> >
> > Leads to a crash on boot during selftest on a vlsseg8e32.v instruction,
> > because it requires 4-byte alignment of the buffers.
> >
> > OpenSBI by default emulates vector misaligned operations, however Linux
> > explicitly disables it with SBI FWFT while not providing vector
> > misaligned emulation of its own.
> >
> > This can be reproduced by running everything in Spike without
> > --misaligned, and is reproducible on stable 6.17.9, 6.18-rc1 and
> > 6.18-rc7. See log at the end. Note that I had to fix chacha_zvkb
> > somewhat to have it retain a frame pointer to get a stack trace - patch
> > will be sent later.
> >
> > Setting cra_alignmask to 3 for everything in crypto/chacha.c "fixes"
> > this, but there seems to be no obvious way to say "if use_zvkb then
> > cra_alignmask = 3", and, not being familiar with the crypto API stuff, I
> > can't figure out a good way to say "if riscv then cra_alignmask = 3" either.
> >
> > AFAICT, this problem was missed from the very start since commit
> > bb54668837a0 ("crypto: riscv - add vector crypto accelerated ChaCha20").
> >
> > Please advise.
> >
> 
> I'd suggest to only enable this version of the code if both Zicclsm
> and Zvkb are supported (assuming that Zicclsm is the extension that
> would result in these misaligned accesses to be permitted).
> 
> Playing with the cra_alignmask is likely insufficient, because it does
> not fix the use cases that call the library interface directly.

Yes, we should make all the RISC-V vector crypto code (i.e., anything in
lib/crypto/riscv/ and arch/riscv/crypto/ that uses vector instructions)
be enabled only when the CPU supports fast misaligned vector accesses.
That was the original intent, but it seems the check never actually made
it into the code because it predated the core RISC-V support for
detecting that capability.

That support later got added by the following commit:

    commit e7c9d66e313bc0f7cb185c4972c3c9383a0da70f
    Author: Jesse Taube <jesse@rivosinc.com>
    Date:   Thu Oct 17 12:00:22 2024 -0700

        RISC-V: Report vector unaligned access speed hwprobe

Note that Zicclsm is supposedly not the correct thing to check.  See
https://lore.kernel.org/linux-riscv/20231122-displace-reformat-9ca68c3dc66c@spud/

It looks like all the RISC-V crypto code needs to check for
this_cpu_read(vector_misaligned_access) ==
RISCV_HWPROBE_MISALIGNED_VECTOR_FAST.
But it may be in need of a helper function.

Any volunteers?  Again, many files need this, not just the ChaCha code.

- Eric