[PATCH v2 0/2] lib/crypto: x86/sha: Add PHE Extensions support

[PATCH v2 0/2] lib/crypto: x86/sha: Add PHE Extensions support

[AlanSong-oc]

For Zhaoxin processors, the XSHA1 instruction requires the total memory
allocated at %rdi register must be 32 bytes, while the XSHA1 and
XSHA256 instruction doesn't perform any operation when %ecx is zero.

Due to these requirements, the current padlock-sha driver does not work
correctly with Zhaoxin processors. It cannot pass the self-tests and
therefore does not activate the driver on Zhaoxin processors. This issue
has been reported in Debian [1]. The self-tests fail with the
following messages [2]:

alg: shash: sha1-padlock-nano test failed (wrong result) on test vector 0, cfg="init+update+final aligned buffer"
alg: self-tests for sha1 using sha1-padlock-nano failed (rc=-22)
------------[ cut here ]------------

alg: shash: sha256-padlock-nano test failed (wrong result) on test vector 0, cfg="init+update+final aligned buffer"
alg: self-tests for sha256 using sha256-padlock-nano failed (rc=-22)
------------[ cut here ]------------

To enable XSHA1 and XSHA256 instruction support on Zhaoxin processors,
this series adds PHE Extensions support to lib/crypto for SHA-1 and
SHA-256, following the suggestion in [3].

v1 link is below:
https://lore.kernel.org/linux-crypto/20250611101750.6839-1-AlanSong-oc@zhaoxin.com/

---
v1->v2: Add Zhaoxin support to lib/crypto instead of extending
        the existing padlock-sha driver

[1] https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1103397
[2] https://linux-hardware.org/?probe=271fabb7a4&log=dmesg
[3] https://lore.kernel.org/linux-crypto/aUI4CGp6kK7mxgEr@gondor.apana.org.au/

AlanSong-oc (2):
  lib/crypto: x86/sha1: PHE Extensions optimized SHA1 transform function
  lib/crypto: x86/sha256: PHE Extensions optimized SHA256 transform
    function

 lib/crypto/Makefile             |  6 ++-
 lib/crypto/x86/sha1-phe-asm.S   | 71 +++++++++++++++++++++++++++++++++
 lib/crypto/x86/sha1.h           | 20 ++++++++++
 lib/crypto/x86/sha256-phe-asm.S | 70 ++++++++++++++++++++++++++++++++
 lib/crypto/x86/sha256.h         | 20 ++++++++++
 5 files changed, 185 insertions(+), 2 deletions(-)
 create mode 100644 lib/crypto/x86/sha1-phe-asm.S
 create mode 100644 lib/crypto/x86/sha256-phe-asm.S

-- 
2.34.1

[PATCH v2 1/2] lib/crypto: x86/sha1: PHE Extensions optimized SHA1 transform function

[AlanSong-oc]

Zhaoxin CPUs have implemented the SHA(Secure Hash Algorithm) as its CPU
instructions by PHE(Padlock Hash Engine) Extensions, including XSHA1,
XSHA256, XSHA384 and XSHA512 instructions.

With the help of implementation of SHA in hardware instead of software,
can develop applications with higher performance, more security and more
flexibility.

This patch includes the XSHA1 instruction optimized implementation of
SHA-1 transform function.

Signed-off-by: AlanSong-oc <AlanSong-oc@zhaoxin.com>
---
 lib/crypto/Makefile           |  3 +-
 lib/crypto/x86/sha1-phe-asm.S | 71 +++++++++++++++++++++++++++++++++++
 lib/crypto/x86/sha1.h         | 20 ++++++++++
 3 files changed, 93 insertions(+), 1 deletion(-)
 create mode 100644 lib/crypto/x86/sha1-phe-asm.S

diff --git a/lib/crypto/Makefile b/lib/crypto/Makefile
index d2845b214..069069377 100644
--- a/lib/crypto/Makefile
+++ b/lib/crypto/Makefile
@@ -205,7 +205,8 @@ endif
 libsha1-$(CONFIG_SPARC) += sparc/sha1_asm.o
 libsha1-$(CONFIG_X86) += x86/sha1-ssse3-and-avx.o \
 			 x86/sha1-avx2-asm.o \
-			 x86/sha1-ni-asm.o
+			 x86/sha1-ni-asm.o \
+			 x86/sha1-phe-asm.o
 endif # CONFIG_CRYPTO_LIB_SHA1_ARCH
 
 ################################################################################
diff --git a/lib/crypto/x86/sha1-phe-asm.S b/lib/crypto/x86/sha1-phe-asm.S
new file mode 100644
index 000000000..eff086104
--- /dev/null
+++ b/lib/crypto/x86/sha1-phe-asm.S
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * PHE Extensions optimized implementation of a SHA-1 update function
+ *
+ * This file is provided under a dual BSD/GPLv2 license.  When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * BSD LICENSE
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 	* Redistributions of source code must retain the above copyright
+ * 	  notice, this list of conditions and the following disclaimer.
+ * 	* Redistributions in binary form must reproduce the above copyright
+ * 	  notice, this list of conditions and the following disclaimer in
+ * 	  the documentation and/or other materials provided with the
+ * 	  distribution.
+ * 	* Neither the name of Intel Corporation nor the names of its
+ * 	  contributors may be used to endorse or promote products derived
+ * 	  from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <linux/linkage.h>
+
+/*
+ * PHE Extensions optimized implementation of a SHA-1 block function
+ *
+ * This function takes a pointer to the current SHA-1 state, a pointer to the
+ * input data, and the number of 64-byte blocks to process.  The number of
+ * blocks to process is assumed to be nonzero.  Once all blocks have been
+ * processed, the state is updated with the new state.  This function only
+ * processes complete blocks.  State initialization, buffering of partial
+ * blocks, and digest finalization are expected to be handled elsewhere.
+ *
+ * void sha1_transform_phe(u8 *state, const u8 *data, size_t nblocks)
+ */
+.text
+SYM_FUNC_START(sha1_transform_phe)
+	mov		$-1, %rax
+	mov		%rdx, %rcx
+
+	.byte	0xf3,0x0f,0xa6,0xc8
+
+	RET
+SYM_FUNC_END(sha1_transform_phe)
diff --git a/lib/crypto/x86/sha1.h b/lib/crypto/x86/sha1.h
index c48a0131f..670109c79 100644
--- a/lib/crypto/x86/sha1.h
+++ b/lib/crypto/x86/sha1.h
@@ -48,6 +48,23 @@ static void sha1_blocks_avx2(struct sha1_block_state *state,
 	}
 }
 
+#define PHE_ALIGNMENT 16
+asmlinkage void sha1_transform_phe(u8 *state, const u8 *data, size_t nblocks);
+static void sha1_blocks_phe(struct sha1_block_state *state,
+			     const u8 *data, size_t nblocks)
+{
+	/*
+	 * XSHA1 requires %edi to point to a 32-byte, 16-byte-aligned
+	 * buffer on Zhaoxin processors.
+	 */
+	u8 buf[32 + PHE_ALIGNMENT - 1];
+	u8 *dst = PTR_ALIGN(&buf[0], PHE_ALIGNMENT);
+
+	memcpy(dst, (u8 *)(state), SHA1_DIGEST_SIZE);
+	sha1_transform_phe(dst, data, nblocks);
+	memcpy((u8 *)(state), dst, SHA1_DIGEST_SIZE);
+}
+
 static void sha1_blocks(struct sha1_block_state *state,
 			const u8 *data, size_t nblocks)
 {
@@ -59,6 +76,9 @@ static void sha1_mod_init_arch(void)
 {
 	if (boot_cpu_has(X86_FEATURE_SHA_NI)) {
 		static_call_update(sha1_blocks_x86, sha1_blocks_ni);
+	} else if (boot_cpu_has(X86_FEATURE_PHE) && boot_cpu_has(X86_FEATURE_PHE_EN)) {
+		if (cpu_data(0).x86 >= 0x07)
+			static_call_update(sha1_blocks_x86, sha1_blocks_phe);
 	} else if (cpu_has_xfeatures(XFEATURE_MASK_SSE | XFEATURE_MASK_YMM,
 				     NULL) &&
 		   boot_cpu_has(X86_FEATURE_AVX)) {
-- 
2.34.1

[PATCH v2 2/2] lib/crypto: x86/sha256: PHE Extensions optimized SHA256 transform function

[AlanSong-oc]

Zhaoxin CPUs have implemented the SHA(Secure Hash Algorithm) as its CPU
instructions by PHE(Padlock Hash Engine) Extensions, including XSHA1,
XSHA256, XSHA384 and XSHA512 instructions.

With the help of implementation of SHA in hardware instead of software,
can develop applications with higher performance, more security and more
flexibility.

This patch includes the XSHA256 instruction optimized implementation of
SHA-256 transform function.

Signed-off-by: AlanSong-oc <AlanSong-oc@zhaoxin.com>
---
 lib/crypto/Makefile             |  3 +-
 lib/crypto/x86/sha256-phe-asm.S | 70 +++++++++++++++++++++++++++++++++
 lib/crypto/x86/sha256.h         | 20 ++++++++++
 3 files changed, 92 insertions(+), 1 deletion(-)
 create mode 100644 lib/crypto/x86/sha256-phe-asm.S

diff --git a/lib/crypto/Makefile b/lib/crypto/Makefile
index 069069377..f56c6e6c7 100644
--- a/lib/crypto/Makefile
+++ b/lib/crypto/Makefile
@@ -236,7 +236,8 @@ libsha256-$(CONFIG_SPARC) += sparc/sha256_asm.o
 libsha256-$(CONFIG_X86) += x86/sha256-ssse3-asm.o \
 			   x86/sha256-avx-asm.o \
 			   x86/sha256-avx2-asm.o \
-			   x86/sha256-ni-asm.o
+			   x86/sha256-ni-asm.o \
+			   x86/sha256-phe-asm.o
 endif # CONFIG_CRYPTO_LIB_SHA256_ARCH
 
 ################################################################################
diff --git a/lib/crypto/x86/sha256-phe-asm.S b/lib/crypto/x86/sha256-phe-asm.S
new file mode 100644
index 000000000..404c6bed7
--- /dev/null
+++ b/lib/crypto/x86/sha256-phe-asm.S
@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * PHE Extensions optimized implementation of a SHA-1 update function
+ *
+ * This file is provided under a dual BSD/GPLv2 license.  When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * BSD LICENSE
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 	* Redistributions of source code must retain the above copyright
+ * 	  notice, this list of conditions and the following disclaimer.
+ * 	* Redistributions in binary form must reproduce the above copyright
+ * 	  notice, this list of conditions and the following disclaimer in
+ * 	  the documentation and/or other materials provided with the
+ * 	  distribution.
+ * 	* Neither the name of Intel Corporation nor the names of its
+ * 	  contributors may be used to endorse or promote products derived
+ * 	  from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <linux/linkage.h>
+
+/*
+ * PHE Extensions optimized implementation of a SHA-256 block function
+ *
+ * This function takes a pointer to the current SHA-256 state, a pointer to the
+ * input data, and the number of 64-byte blocks to process.  Once all blocks
+ * have been processed, the state is updated with the new state.  This function
+ * only processes complete blocks.  State initialization, buffering of partial
+ * blocks, and digest finalization is expected to be handled elsewhere.
+ *
+ * void sha256_transform_phe(u8 *state, const u8 *data, size_t nblocks)
+ */
+.text
+SYM_FUNC_START(sha256_transform_phe)
+	mov		$-1, %rax
+	mov		%rdx, %rcx
+
+	.byte	0xf3,0x0f,0xa6,0xd0
+
+	RET
+SYM_FUNC_END(sha256_transform_phe)
diff --git a/lib/crypto/x86/sha256.h b/lib/crypto/x86/sha256.h
index 38e33b22a..072b44480 100644
--- a/lib/crypto/x86/sha256.h
+++ b/lib/crypto/x86/sha256.h
@@ -31,6 +31,23 @@ DEFINE_X86_SHA256_FN(sha256_blocks_avx, sha256_transform_avx);
 DEFINE_X86_SHA256_FN(sha256_blocks_avx2, sha256_transform_rorx);
 DEFINE_X86_SHA256_FN(sha256_blocks_ni, sha256_ni_transform);
 
+#define PHE_ALIGNMENT 16
+asmlinkage void sha256_transform_phe(u8 *state, const u8 *data, size_t nblocks);
+static void sha256_blocks_phe(struct sha256_block_state *state,
+			     const u8 *data, size_t nblocks)
+{
+	/*
+	 * XSHA256 requires %edi to point to a 32-byte, 16-byte-aligned
+	 * buffer on Zhaoxin processors.
+	 */
+	u8 buf[32 + PHE_ALIGNMENT - 1];
+	u8 *dst = PTR_ALIGN(&buf[0], PHE_ALIGNMENT);
+
+	memcpy(dst, (u8 *)(state), SHA256_DIGEST_SIZE);
+	sha256_transform_phe(dst, data, nblocks);
+	memcpy((u8 *)(state), dst, SHA256_DIGEST_SIZE);
+}
+
 static void sha256_blocks(struct sha256_block_state *state,
 			  const u8 *data, size_t nblocks)
 {
@@ -79,6 +96,9 @@ static void sha256_mod_init_arch(void)
 	if (boot_cpu_has(X86_FEATURE_SHA_NI)) {
 		static_call_update(sha256_blocks_x86, sha256_blocks_ni);
 		static_branch_enable(&have_sha_ni);
+	} else if (boot_cpu_has(X86_FEATURE_PHE) && boot_cpu_has(X86_FEATURE_PHE_EN)) {
+		if (cpu_data(0).x86 >= 0x07)
+			static_call_update(sha256_blocks_x86, sha256_blocks_phe);
 	} else if (cpu_has_xfeatures(XFEATURE_MASK_SSE | XFEATURE_MASK_YMM,
 				     NULL) &&
 		   boot_cpu_has(X86_FEATURE_AVX)) {
-- 
2.34.1

Re: [PATCH v2 1/2] lib/crypto: x86/sha1: PHE Extensions optimized SHA1 transform function

[Eric Biggers]

[+Cc x86@kernel.org]

On Fri, Dec 19, 2025 at 04:03:05PM +0800, AlanSong-oc wrote:
> diff --git a/lib/crypto/Makefile b/lib/crypto/Makefile
> index d2845b214..069069377 100644
> --- a/lib/crypto/Makefile
> +++ b/lib/crypto/Makefile
> @@ -205,7 +205,8 @@ endif
>  libsha1-$(CONFIG_SPARC) += sparc/sha1_asm.o
>  libsha1-$(CONFIG_X86) += x86/sha1-ssse3-and-avx.o \
>  			 x86/sha1-avx2-asm.o \
> -			 x86/sha1-ni-asm.o
> +			 x86/sha1-ni-asm.o \
> +			 x86/sha1-phe-asm.o
>  endif # CONFIG_CRYPTO_LIB_SHA1_ARCH
>  
>  ################################################################################
> diff --git a/lib/crypto/x86/sha1-phe-asm.S b/lib/crypto/x86/sha1-phe-asm.S
> new file mode 100644
> index 000000000..eff086104
> --- /dev/null
> +++ b/lib/crypto/x86/sha1-phe-asm.S
> @@ -0,0 +1,71 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * PHE Extensions optimized implementation of a SHA-1 update function
> + *
> + * This file is provided under a dual BSD/GPLv2 license.  When using or
> + * redistributing this file, you may do so under either license.
> + *
> + * GPL LICENSE SUMMARY
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of version 2 of the GNU General Public License as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful, but
> + * WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * General Public License for more details.
> + *
> + * BSD LICENSE
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + *
> + * 	* Redistributions of source code must retain the above copyright
> + * 	  notice, this list of conditions and the following disclaimer.
> + * 	* Redistributions in binary form must reproduce the above copyright
> + * 	  notice, this list of conditions and the following disclaimer in
> + * 	  the documentation and/or other materials provided with the
> + * 	  distribution.
> + * 	* Neither the name of Intel Corporation nor the names of its
> + * 	  contributors may be used to endorse or promote products derived
> + * 	  from this software without specific prior written permission.
> + *
> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
> + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
> + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
> + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
> + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
> + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
> + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
> + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
> + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
> + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + *
> + */
> +
> +#include <linux/linkage.h>
> +
> +/*
> + * PHE Extensions optimized implementation of a SHA-1 block function
> + *
> + * This function takes a pointer to the current SHA-1 state, a pointer to the
> + * input data, and the number of 64-byte blocks to process.  The number of
> + * blocks to process is assumed to be nonzero.  Once all blocks have been
> + * processed, the state is updated with the new state.  This function only
> + * processes complete blocks.  State initialization, buffering of partial
> + * blocks, and digest finalization are expected to be handled elsewhere.
> + *
> + * void sha1_transform_phe(u8 *state, const u8 *data, size_t nblocks)
> + */
> +.text
> +SYM_FUNC_START(sha1_transform_phe)
> +	mov		$-1, %rax
> +	mov		%rdx, %rcx
> +
> +	.byte	0xf3,0x0f,0xa6,0xc8
> +
> +	RET
> +SYM_FUNC_END(sha1_transform_phe)

Please make this an inline asm statement instead of using a .S file.
It's just one instruction.

> +#define PHE_ALIGNMENT 16
> +asmlinkage void sha1_transform_phe(u8 *state, const u8 *data, size_t nblocks);
> +static void sha1_blocks_phe(struct sha1_block_state *state,
> +			     const u8 *data, size_t nblocks)
> +{
> +	/*
> +	 * XSHA1 requires %edi to point to a 32-byte, 16-byte-aligned
> +	 * buffer on Zhaoxin processors.
> +	 */

What is the largest 'nblocks' that the instruction supports?

What happens if the instruction is interrupted partway through?  Does
the CPU correctly resume it in all cases?

Is it supported in both 32-bit and 64-bit modes?  Your patch doesn't
check for CONFIG_64BIT.  Should it?  New optimized assembly code
generally should be 64-bit only.

Where is this instruction specified?  Please add a comment that links to
the specification.

> +	u8 buf[32 + PHE_ALIGNMENT - 1];
> +	u8 *dst = PTR_ALIGN(&buf[0], PHE_ALIGNMENT);
> +
> +	memcpy(dst, (u8 *)(state), SHA1_DIGEST_SIZE);
> +	sha1_transform_phe(dst, data, nblocks);
> +	memcpy((u8 *)(state), dst, SHA1_DIGEST_SIZE);
> +}

The casts to 'u8 *' are unnecessary.

> +
>  static void sha1_blocks(struct sha1_block_state *state,
>  			const u8 *data, size_t nblocks)
>  {
> @@ -59,6 +76,9 @@ static void sha1_mod_init_arch(void)
>  {
>  	if (boot_cpu_has(X86_FEATURE_SHA_NI)) {
>  		static_call_update(sha1_blocks_x86, sha1_blocks_ni);
> +	} else if (boot_cpu_has(X86_FEATURE_PHE) && boot_cpu_has(X86_FEATURE_PHE_EN)) {
> +		if (cpu_data(0).x86 >= 0x07)
> +			static_call_update(sha1_blocks_x86, sha1_blocks_phe);

Check IS_ENABLED(CONFIG_CPU_SUP_ZHAOXIN) first, so that the code gets
compiled out when support for Zhaoxin CPUs isn't included in the kernel.

There are hardly any mentions of 'cpu_data(0).x86' in the kernel.  I
think you mean 'boot_cpu_data.x86', which is used much more frequently.

What is the difference between X86_FEATURE_PHE and X86_FEATURE_PHE_EN,
and why are both needed?

All these comments apply to the SHA-256 patch too.

- Eric

Re: [PATCH v2 0/2] lib/crypto: x86/sha: Add PHE Extensions support

[Eric Biggers]

On Fri, Dec 19, 2025 at 04:03:04PM +0800, AlanSong-oc wrote:
> For Zhaoxin processors, the XSHA1 instruction requires the total memory
> allocated at %rdi register must be 32 bytes, while the XSHA1 and
> XSHA256 instruction doesn't perform any operation when %ecx is zero.
> 
> Due to these requirements, the current padlock-sha driver does not work
> correctly with Zhaoxin processors. It cannot pass the self-tests and
> therefore does not activate the driver on Zhaoxin processors. This issue
> has been reported in Debian [1]. The self-tests fail with the
> following messages [2]:
> 
> alg: shash: sha1-padlock-nano test failed (wrong result) on test vector 0, cfg="init+update+final aligned buffer"
> alg: self-tests for sha1 using sha1-padlock-nano failed (rc=-22)
> ------------[ cut here ]------------
> 
> alg: shash: sha256-padlock-nano test failed (wrong result) on test vector 0, cfg="init+update+final aligned buffer"
> alg: self-tests for sha256 using sha256-padlock-nano failed (rc=-22)
> ------------[ cut here ]------------

This cover letter is misleading, as those self-test failures will still
exist regardless of this patch series.

> To enable XSHA1 and XSHA256 instruction support on Zhaoxin processors,
> this series adds PHE Extensions support to lib/crypto for SHA-1 and
> SHA-256, following the suggestion in [3].
> 
> v1 link is below:
> https://lore.kernel.org/linux-crypto/20250611101750.6839-1-AlanSong-oc@zhaoxin.com/

Please run the sha1 and sha256 KUnit test suites
(CRYPTO_LIB_SHA1_KUNIT_TEST and CRYPTO_LIB_SHA256_KUNIT_TEST) before and
after this series, with the benchmark enabled (CRYPTO_LIB_BENCHMARK),
and show the results.  For this series to be considered, the tests need
to pass and there needs to be a significant performance improvement.

- Eric