From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F9463BFE40; Fri, 10 Apr 2026 12:19:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775823555; cv=none; b=UPss8nVAuMTAN3pnwUYX6yCZ7+jJvr73arfBZPYO+xfwireSSUjyXhJH5TGQ2piRT0WZ92UY7H4aQYrc7Qc8Cit5Y9Q5MA5vJJm9sY507ms2K6bYHWG+JcnaZWwfSTv1kk9NrryoJL3WAkgfkOi6yy0gieHgOqbowiG02E8toGI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775823555; c=relaxed/simple; bh=qtG4jYoFMBUH8Rv5LkkLsBrvbBwuDbTX1269QfkLCzw=; h=Date:Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type; b=NuZWGs7c9F/nxYYh4xjAHr15mr+jzC5d2SbzM+zhw7jfOaF+82PzmSsSMf8h9ydKzttuf868rQzsgbwMXH/vxT5bnYS7OCppCwbArnZR/UoKblIV+tH7WwMhHqTjeR08UbE5jTwi+0XeOJrDD2f626jOLL4+5inCrBf4sWCCJtE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=pacXAmHL; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pacXAmHL" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8BE3EC2BC87; Fri, 10 Apr 2026 12:19:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775823555; bh=qtG4jYoFMBUH8Rv5LkkLsBrvbBwuDbTX1269QfkLCzw=; h=Date:From:To:Cc:Subject:References:From; b=pacXAmHLAMseTev4RAQUAZDfRzJFeJXjwMW3x14w8vUm7ybikBbtslQQu96s/8Sq0 a3pcIexn/gzfbwI2qYLuXSTx/gSXbmVwhuUFKfTY31pSFVH71nhoebkIPAnwJfmArK tPmJiCD8oWRaoY6EByg0L3DGpV75oKKW/C5lmUUCoaSznEsjUHpS9yyQByZ5hUlH3x P8NYw39byMTR2ebfPveTfvTFbDgwqYFvegEj7/kJQbjlvVeppRrN8YtOduabfxNT6E Yw4oV6JDjGSLEpWghPJGJFmnCci2PXJh9wjpVWvhGUbODkplfUDbeuEJIVIN1zibiF mC2OEaJT1jHhg== Date: Fri, 10 Apr 2026 14:19:12 +0200 Message-ID: <20260410120318.187521447@kernel.org> User-Agent: quilt/0.68 From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Lu Baolu , iommu@lists.linux.dev, Arnd Bergmann , Michael Grzeschik , netdev@vger.kernel.org, linux-wireless@vger.kernel.org, Herbert Xu , linux-crypto@vger.kernel.org, Vlastimil Babka , linux-mm@kvack.org, David Woodhouse , Bernie Thompson , linux-fbdev@vger.kernel.org, "Theodore Tso" , linux-ext4@vger.kernel.org, Andrew Morton , Uladzislau Rezki , Marco Elver , Dmitry Vyukov , kasan-dev@googlegroups.com, Andrey Ryabinin , Thomas Sailer , linux-hams@vger.kernel.org, "Jason A. Donenfeld" , Richard Henderson , linux-alpha@vger.kernel.org, Russell King , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Huacai Chen , loongarch@lists.linux.dev, Geert Uytterhoeven , linux-m68k@lists.linux-m68k.org, Dinh Nguyen , Jonas Bonn , linux-openrisc@vger.kernel.org, Helge Deller , linux-parisc@vger.kernel.org, Michael Ellerman , linuxppc-dev@lists.ozlabs.org, Paul Walmsley , linux-riscv@lists.infradead.org, Heiko Carstens , linux-s390@vger.kernel.org, "David S. Miller" , sparclinux@vger.kernel.org Subject: [patch 09/38] iommu/vt-d: Use sched_clock() instead of get_cycles() References: <20260410120044.031381086@kernel.org> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Calculating the timeout from get_cycles() is a historical leftover without any functional requirement. Use ktime_get() instead. Signed-off-by: Thomas Gleixner Cc: x86@kernel.org Cc: Lu Baolu Cc: iommu@lists.linux.dev --- arch/x86/include/asm/iommu.h | 3 --- drivers/iommu/intel/dmar.c | 4 ++-- drivers/iommu/intel/iommu.h | 8 ++++++-- 3 files changed, 8 insertions(+), 7 deletions(-) --- a/arch/x86/include/asm/iommu.h +++ b/arch/x86/include/asm/iommu.h @@ -18,9 +18,6 @@ extern bool x86_swiotlb_enable; #define x86_swiotlb_enable false #endif -/* 10 seconds */ -#define DMAR_OPERATION_TIMEOUT ((cycles_t) tsc_khz*10*1000) - static inline int __init arch_rmrr_sanity_check(struct acpi_dmar_reserved_memory *rmrr) { --- a/drivers/iommu/intel/dmar.c +++ b/drivers/iommu/intel/dmar.c @@ -1606,9 +1606,9 @@ void qi_flush_pasid_cache(struct intel_i */ void dmar_disable_qi(struct intel_iommu *iommu) { + ktime_t start_time = ktime_get(); unsigned long flags; u32 sts; - cycles_t start_time = get_cycles(); if (!ecap_qis(iommu->ecap)) return; @@ -1624,7 +1624,7 @@ void dmar_disable_qi(struct intel_iommu */ while ((readl(iommu->reg + DMAR_IQT_REG) != readl(iommu->reg + DMAR_IQH_REG)) && - (DMAR_OPERATION_TIMEOUT > (get_cycles() - start_time))) + (DMAR_OPERATION_TIMEOUT > (ktime_get() - start_time))) cpu_relax(); iommu->gcmd &= ~DMA_GCMD_QIE; --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -23,6 +23,7 @@ #include #include #include +#include #include #include @@ -360,14 +361,17 @@ /* PERFINTRSTS_REG */ #define DMA_PERFINTRSTS_PIS ((u32)1) +#define DMAR_OPERATION_TIMEOUT (((ktime_t)10) * NSEC_PER_SEC) + #define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \ do { \ - cycles_t start_time = get_cycles(); \ + ktime_t start_time = ktime_get(); \ + \ while (1) { \ sts = op(iommu->reg + offset); \ if (cond) \ break; \ - if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\ + if (DMAR_OPERATION_TIMEOUT < (ktime_get() - start_time))\ panic("DMAR hardware is malfunctioning\n"); \ cpu_relax(); \ } \