From: "lianfeng.ouyang" <lianfeng.ouyang@starfivetech.com>
To: Olivia Mackall <olivia@selenic.com>,
Herbert Xu <herbert@gondor.apana.org.au>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>
Cc: linux-crypto@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v1 0/2] Add trng driver to JHB100
Date: Tue, 12 May 2026 14:24:02 +0800 [thread overview]
Message-ID: <20260512062404.4540-1-lianfeng.ouyang@starfivetech.com> (raw)
From: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
for jhb100, While IP assert async reset, it may generate glitch
and propagate to downstream IP. In order to solve RDC issue,
conduct clock gating before asserting reset to prevent generating glitch.
Lianfeng Ouyang (2):
dt-bindings: Add bindings for StarFive JHB100 SoC trng controller.
hwrng: starfive: Update clk and reset sequence
.../bindings/rng/starfive,jh7110-trng.yaml | 2 +-
MAINTAINERS | 2 +-
drivers/char/hw_random/jh7110-trng.c | 18 ++++++++++++++++--
3 files changed, 18 insertions(+), 4 deletions(-)
--
2.43.0
next reply other threads:[~2026-05-12 6:24 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-12 6:24 lianfeng.ouyang [this message]
2026-05-12 6:24 ` [PATCH v1 1/2] dt-bindings: Add bindings for StarFive JHB100 SoC trng controller lianfeng.ouyang
2026-05-12 17:15 ` Conor Dooley
2026-05-12 19:35 ` Conor Dooley
2026-05-12 6:24 ` [PATCH v1 2/2] hwrng: starfive: Update clk and reset sequence lianfeng.ouyang
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