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Miller" CC: Manorit Chawdhry , Kamlesh Gurudasani , Shiva Tripathi , Kavitha Malarvizhi , Vishal Mahaveer , Praneeth Bajjuri , , Subject: [PATCH v4 3/3] crypto: ti - Add support for HMAC in DTHEv2 Hashing Engine driver Date: Tue, 26 May 2026 15:13:53 +0530 Message-ID: <20260526094355.555712-4-t-pratham@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260526094355.555712-1-t-pratham@ti.com> References: <20260526094355.555712-1-t-pratham@ti.com> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE31:EE_|CO1PR10MB4740:EE_ X-MS-Office365-Filtering-Correlation-Id: ab3f4a4a-5302-4b2d-d19d-08debb0b7b21 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700016|22082099003|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: 37V4BAbmtb9Z1ipMoLe4JYNUc2B2RLQwspPKcbwq2XyYcvyUlkcSkBTaRDIGcpo9d2axo/9TVhzTAkHILXs/zX0kUl6OEfiNpt981NBoH9EqsNPUGhGUmk38mjQ6/55LLZfKFaFWd6FA1qQHn1/ZHugZ73QpOWa//KKak0JsdPmzHyhLEI60Gt/XXuzZnVXAJegyD48PH262yvsf9nfXSxpWTaTXuCbASehOCsij0LsPi8BTQ7pCWHIR0dGke8b3eSdK+TI8wwAJNFdNMRKCm5aVzloiGm9tfeheYDkU5wNBsYDzy1MOt+OLvOU1XInKvGPoFP/Tyo2pb0mzTZtVyEgO2FgyuFiWW03+pumQjD2nYWdSa56mNXVGjU6lwqNVAQ355VVDWTyGY9s4/FyaI2mYHPbnpSY920xD4bjGZWCljJhKgI03QdaNgWXm0Fxs5o/L/kbC4l0zUyfT/pZvynDA1ZnmIsP0ym07GtY17NENyU8XlSVLP2WOKpnILUxLg/kl3pAbVSs4qJUmAF7EP2faxyTggh8lZrB1a04Mg6qnbYJbG4C67CiOZUeuwiEscld3fPH+kGQpBSQy7tbVg8nxWxajphRDkLQvT0ihMCvhy3Ljf4VnGDZQiG4rkC2CrqMSOJpAA08RAzrvacqv7bvnYvIpAoKF/HoHMnZw7krZ4JZ6BG9Kjv2biSKYh72uHhMyTEEPUQpG2LrtOaJxhMnURiqQAlsQS/9rKEH0qjs= X-Forefront-Antispam-Report: CIP:198.47.23.195;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:lewvzet201.ext.ti.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(82310400026)(36860700016)(22082099003)(56012099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: MdNveIukmVs4Cc4OW9FVPEa+h8yaB5KDBtm+28DLDQr4+fd/fn2HYijFj61CQQq1vdwzGn/7hX2EVg6r36etlUyPm9/Egx2cIvyx7564oTSGmieJ5PTIsVRabXej93wfVXUI5PSCWCiTtDZv+XjPdhciUyNW0BvYpgiEBJ9BIE8+DzwVDqJXVIk/6n6yisWb45ASUyVsVNmj2hKp9Wwqfbpu55LogPvq1+5HUtZSTPkuynQKNIi3gQtk1W7SRMGT+Ld41SNmbCYMl2XKK8P/yWNEW3aDt+MkQ+RybSf5KPg9xbbJ9+a1VwBhQdLn0cYHuCSOKeR099RkeJcwcWJR2jhFFirtamA3R8yucoF4Uc+CEgky/1IFLp0oCtO3KgFmolfihYr3xprpcIvTBsa6pZ8rS/0FsL1Hdli4SbW/DjyPNmw0djhu/+HUZcCBhmW/ X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 May 2026 09:45:11.7205 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ab3f4a4a-5302-4b2d-d19d-08debb0b7b21 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.195];Helo=[lewvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE31.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO1PR10MB4740 Add support for HMAC-SHA512/384/256/224 and HMAC-MD5 algorithms in the hashing engine of the DTHEv2 hardware cryptographic engine. Signed-off-by: T Pratham --- drivers/crypto/ti/Kconfig | 1 + drivers/crypto/ti/dthev2-common.h | 10 +- drivers/crypto/ti/dthev2-hash.c | 346 +++++++++++++++++++++++++++++- 3 files changed, 351 insertions(+), 6 deletions(-) diff --git a/drivers/crypto/ti/Kconfig b/drivers/crypto/ti/Kconfig index 9c2aa50cfbfbe..68dccf92f5382 100644 --- a/drivers/crypto/ti/Kconfig +++ b/drivers/crypto/ti/Kconfig @@ -13,6 +13,7 @@ config CRYPTO_DEV_TI_DTHEV2 select CRYPTO_SHA256 select CRYPTO_SHA512 select CRYPTO_MD5 + select CRYPTO_HMAC select SG_SPLIT help This enables support for the TI DTHE V2 hw cryptography engine diff --git a/drivers/crypto/ti/dthev2-common.h b/drivers/crypto/ti/dthev2-common.h index 24799007ea81f..847804ed74736 100644 --- a/drivers/crypto/ti/dthev2-common.h +++ b/drivers/crypto/ti/dthev2-common.h @@ -31,9 +31,9 @@ #define DTHE_DMA_TIMEOUT_MS 2000 /* * Size of largest possible key (of all algorithms) to be stored in dthe_tfm_ctx - * This is currently the keysize of XTS-AES-256 which is 512 bits (64 bytes) + * This is currently the keysize of HMAC-SHA512 which is 1024 bits (128 bytes) */ -#define DTHE_MAX_KEYSIZE (AES_MAX_KEY_SIZE * 2) +#define DTHE_MAX_KEYSIZE (SHA512_BLOCK_SIZE) enum dthe_hash_alg_sel { DTHE_HASH_MD5 = 0, @@ -93,9 +93,9 @@ struct dthe_list { /** * struct dthe_tfm_ctx - Transform ctx struct containing ctx for all sub-components of DTHE V2 * @dev_data: Device data struct pointer - * @keylen: AES key length + * @keylen: Key length for algorithms that use a key * @authsize: Authentication size for modes with authentication - * @key: AES key + * @key: Buffer storing the key * @aes_mode: AES mode * @hash_mode: Hashing Engine mode * @phash_size: partial hash size of the hash algorithm selected @@ -135,6 +135,7 @@ struct dthe_aes_req_ctx { * @phash: buffer to store a partial hash from a previous operation * @digestcnt: stores the digest count from a previous operation; currently hardware only provides * a single 32-bit value even for SHA384/512 + * @odigest: buffer to store the outer digest from a previous operation * @phash_available: flag indicating if a partial hash from a previous operation is available * @flags: flags for internal use * @padding: padding buffer for handling unaligned data @@ -143,6 +144,7 @@ struct dthe_aes_req_ctx { struct dthe_hash_req_ctx { u32 phash[SHA512_DIGEST_SIZE / sizeof(u32)]; u64 digestcnt[2]; + u32 odigest[SHA512_DIGEST_SIZE / sizeof(u32)]; u8 phash_available; u8 flags; u8 padding[SHA512_BLOCK_SIZE]; diff --git a/drivers/crypto/ti/dthev2-hash.c b/drivers/crypto/ti/dthev2-hash.c index 4b5df4fdcaa5f..62a42e63c4772 100644 --- a/drivers/crypto/ti/dthev2-hash.c +++ b/drivers/crypto/ti/dthev2-hash.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -23,6 +24,7 @@ /* Registers */ #define DTHE_P_HASH_BASE 0x5000 +#define DTHE_P_HASH512_ODIGEST_A 0x0200 #define DTHE_P_HASH512_IDIGEST_A 0x0240 #define DTHE_P_HASH512_DIGEST_COUNT 0x0280 #define DTHE_P_HASH512_MODE 0x0284 @@ -45,6 +47,13 @@ #define DTHE_HASH_MODE_USE_ALG_CONST BIT(3) #define DTHE_HASH_MODE_CLOSE_HASH BIT(4) +#define DTHE_HASH_MODE_HMAC_KEY_PROCESSING BIT(5) +#define DTHE_HASH_MODE_HMAC_OUTER_HASH BIT(7) + +/* Misc */ +#define DTHE_HMAC_SHA512_MAX_KEYSIZE (SHA512_BLOCK_SIZE) +#define DTHE_HMAC_SHA256_MAX_KEYSIZE (SHA256_BLOCK_SIZE) +#define DTHE_HMAC_MD5_MAX_KEYSIZE (MD5_BLOCK_SIZE) enum dthe_hash_op { DTHE_HASH_OP_UPDATE = 0, @@ -74,6 +83,19 @@ static void dthe_hash_write_zero_message(enum dthe_hash_alg_sel mode, void *dst) } } +static int dthe_hmac_write_zero_message(struct ahash_request *req) +{ + HASH_FBREQ_ON_STACK(fbreq, req); + int ret; + + ahash_request_set_crypt(fbreq, req->src, req->result, + req->nbytes); + + ret = crypto_ahash_digest(fbreq); + HASH_REQUEST_ZERO(fbreq); + return ret; +} + static enum dthe_hash_alg_sel dthe_hash_get_hash_mode(struct crypto_ahash *tfm) { unsigned int ds = crypto_ahash_digestsize(tfm); @@ -131,6 +153,18 @@ static unsigned int dthe_hash_get_phash_size(struct dthe_tfm_ctx *ctx) return phash_size; } +static const char *dthe_hash_get_alg_name(struct dthe_tfm_ctx *ctx) +{ + switch (ctx->hash_mode) { + case DTHE_HASH_SHA224: return "sha224"; + case DTHE_HASH_SHA256: return "sha256"; + case DTHE_HASH_SHA384: return "sha384"; + case DTHE_HASH_SHA512: return "sha512"; + case DTHE_HASH_MD5: return "md5"; + default: return NULL; + } +} + static int dthe_hash_init_tfm(struct crypto_ahash *tfm) { struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(tfm); @@ -184,6 +218,7 @@ static int dthe_hash_dma_start(struct ahash_request *req, struct scatterlist *sr enum dma_data_direction src_dir = DMA_TO_DEVICE; u32 hash_mode; int ds = crypto_ahash_digestsize(tfm); + bool is_hmac = (ctx->keylen > 0); int ret = 0; u32 *dst; u32 dst_len; @@ -229,8 +264,11 @@ static int dthe_hash_dma_start(struct ahash_request *req, struct scatterlist *sr hash_mode = ctx->hash_mode; - if (rctx->flags == DTHE_HASH_OP_FINUP) + if (rctx->flags == DTHE_HASH_OP_FINUP) { hash_mode |= DTHE_HASH_MODE_CLOSE_HASH; + if (is_hmac) + hash_mode |= DTHE_HASH_MODE_HMAC_OUTER_HASH; + } if (rctx->phash_available) { for (int i = 0; i < ctx->phash_size / sizeof(u32); ++i) @@ -238,9 +276,28 @@ static int dthe_hash_dma_start(struct ahash_request *req, struct scatterlist *sr sha_base_reg + DTHE_P_HASH512_IDIGEST_A + (DTHE_REG_SIZE * i)); + if (is_hmac) { + for (int i = 0; i < ctx->phash_size / sizeof(u32); ++i) + writel_relaxed(rctx->odigest[i], + sha_base_reg + + DTHE_P_HASH512_ODIGEST_A + + (DTHE_REG_SIZE * i)); + } writel_relaxed(rctx->digestcnt[0], sha_base_reg + DTHE_P_HASH512_DIGEST_COUNT); + } else if (is_hmac) { + hash_mode |= DTHE_HASH_MODE_HMAC_KEY_PROCESSING; + + for (int i = 0; i < (ctx->keylen / 2) / sizeof(u32); ++i) + writel_relaxed(ctx->key[i], sha_base_reg + + DTHE_P_HASH512_ODIGEST_A + + (DTHE_REG_SIZE * i)); + for (int i = 0; i < (ctx->keylen / 2) / sizeof(u32); ++i) + writel_relaxed(ctx->key[i + (ctx->keylen / 2) / sizeof(u32)], + sha_base_reg + + DTHE_P_HASH512_IDIGEST_A + + (DTHE_REG_SIZE * i)); } else { hash_mode |= DTHE_HASH_MODE_USE_ALG_CONST; } @@ -275,6 +332,12 @@ static int dthe_hash_dma_start(struct ahash_request *req, struct scatterlist *sr dst[i] = readl_relaxed(sha_base_reg + DTHE_P_HASH512_IDIGEST_A + (DTHE_REG_SIZE * i)); + if (is_hmac) { + for (int i = 0; i < dst_len; ++i) + rctx->odigest[i] = readl_relaxed(sha_base_reg + + DTHE_P_HASH512_ODIGEST_A + + (DTHE_REG_SIZE * i)); + } rctx->digestcnt[0] = readl_relaxed(sha_base_reg + DTHE_P_HASH512_DIGEST_COUNT); rctx->phash_available = 1; @@ -399,6 +462,10 @@ static int dthe_hash_final(struct ahash_request *req) return crypto_transfer_hash_request_to_engine(engine, req); } + if (ctx->keylen > 0) + /* HMAC with zero-length message */ + return dthe_hmac_write_zero_message(req); + dthe_hash_write_zero_message(ctx->hash_mode, req->result); return 0; @@ -458,6 +525,53 @@ static const void *dthe_hash_get_init_state(struct dthe_tfm_ctx *ctx) } } +/* + * Compute the HMAC inner or outer pad state (the intermediate hash state after + * processing one block of key XOR pad_byte) and write it to @out. Only the + * first ctx->phash_size bytes are written, which is always the raw hash state + * at the start of the shash export struct. + */ +static int dthe_hmac_compute_pad_state(struct dthe_tfm_ctx *ctx, u8 pad_byte, + void *out) +{ + const char *alg_name = dthe_hash_get_alg_name(ctx); + struct crypto_shash *ktfm; + u8 data[SHA512_BLOCK_SIZE]; + unsigned int ss; + u8 *state; + int ret; + + ktfm = crypto_alloc_shash(alg_name, 0, 0); + if (IS_ERR(ktfm)) + return PTR_ERR(ktfm); + + ss = crypto_shash_statesize(ktfm); + state = kmalloc(ss, GFP_KERNEL); + if (!state) { + crypto_free_shash(ktfm); + return -ENOMEM; + } + + SHASH_DESC_ON_STACK(desc, ktfm); + + desc->tfm = ktfm; + for (int i = 0; i < ctx->keylen; i++) + data[i] = ((u8 *)ctx->key)[i] ^ pad_byte; + + ret = crypto_shash_init(desc) ?: + crypto_shash_update(desc, data, ctx->keylen) ?: + crypto_shash_export(desc, state); + + if (!ret) + memcpy(out, state, ctx->phash_size); + + memzero_explicit(state, ss); + kfree(state); + crypto_free_shash(ktfm); + memzero_explicit(data, sizeof(data)); + return ret; +} + static int dthe_hash_export(struct ahash_request *req, void *out) { struct dthe_hash_req_ctx *rctx = ahash_request_ctx(req); @@ -467,9 +581,12 @@ static int dthe_hash_export(struct ahash_request *req, void *out) u8 *u8; u64 *u64; } p = { .u8 = out }; + int ret = 0; if (rctx->phash_available) memcpy(out, rctx->phash, ctx->phash_size); + else if (ctx->keylen > 0) + ret = dthe_hmac_compute_pad_state(ctx, HMAC_IPAD_VALUE, out); else memcpy(out, dthe_hash_get_init_state(ctx), ctx->phash_size); @@ -478,7 +595,12 @@ static int dthe_hash_export(struct ahash_request *req, void *out) if (ctx->phash_size >= SHA512_DIGEST_SIZE) put_unaligned(rctx->digestcnt[1], p.u64++); - return 0; + if (ctx->keylen > 0) { + memcpy(p.u8, rctx->odigest, ctx->phash_size); + p.u8 += ctx->phash_size; + } + + return ret; } static int dthe_hash_import(struct ahash_request *req, const void *in) @@ -498,9 +620,59 @@ static int dthe_hash_import(struct ahash_request *req, const void *in) rctx->digestcnt[1] = get_unaligned(p.u64++); rctx->phash_available = ((rctx->digestcnt[0]) ? 1 : 0); + if (ctx->keylen > 0) { + memcpy(rctx->odigest, p.u8, ctx->phash_size); + p.u8 += ctx->phash_size; + } + return 0; } +static int dthe_hmac_setkey(struct crypto_ahash *tfm, const u8 *key, + unsigned int keylen) +{ + struct dthe_tfm_ctx *ctx = crypto_ahash_ctx(tfm); + struct crypto_ahash *fb = crypto_ahash_fb(tfm); + const char *hash_alg_name = dthe_hash_get_alg_name(ctx); + unsigned int max_keysize; + + memzero_explicit(ctx->key, sizeof(ctx->key)); + + switch (ctx->hash_mode) { + case DTHE_HASH_SHA512: + case DTHE_HASH_SHA384: + max_keysize = DTHE_HMAC_SHA512_MAX_KEYSIZE; + break; + case DTHE_HASH_SHA256: + case DTHE_HASH_SHA224: + max_keysize = DTHE_HMAC_SHA256_MAX_KEYSIZE; + break; + case DTHE_HASH_MD5: + max_keysize = DTHE_HMAC_MD5_MAX_KEYSIZE; + break; + default: + return -EINVAL; + } + + if (keylen > max_keysize) { + struct crypto_shash *ktfm = crypto_alloc_shash(hash_alg_name, 0, 0); + SHASH_DESC_ON_STACK(desc, ktfm); + int err; + + desc->tfm = ktfm; + err = crypto_shash_digest(desc, key, keylen, (u8 *)ctx->key); + crypto_free_shash(ktfm); + if (err) + return err; + } else { + memcpy(ctx->key, key, keylen); + } + + ctx->keylen = max_keysize; + + return crypto_ahash_setkey(fb, key, keylen); +} + static struct ahash_engine_alg hash_algs[] = { { .base.init_tfm = dthe_hash_init_tfm, @@ -667,6 +839,176 @@ static struct ahash_engine_alg hash_algs[] = { }, .op.do_one_request = dthe_hash_run, }, + { + .base.init_tfm = dthe_hash_init_tfm, + .base.init = dthe_hash_init, + .base.update = dthe_hash_update, + .base.final = dthe_hash_final, + .base.finup = dthe_hash_finup, + .base.digest = dthe_hash_digest, + .base.export = dthe_hash_export, + .base.import = dthe_hash_import, + .base.setkey = dthe_hmac_setkey, + .base.halg = { + .digestsize = SHA512_DIGEST_SIZE, + .statesize = sizeof(struct dthe_hash_req_ctx), + .base = { + .cra_name = "hmac(sha512)", + .cra_driver_name = "hmac-sha512-dthev2", + .cra_priority = 299, + .cra_flags = CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_NEED_FALLBACK | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_FINAL_NONZERO | + CRYPTO_AHASH_ALG_FINUP_MAX | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize = SHA512_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct dthe_tfm_ctx), + .cra_reqsize = sizeof(struct dthe_hash_req_ctx), + .cra_module = THIS_MODULE, + } + }, + .op.do_one_request = dthe_hash_run, + }, + { + .base.init_tfm = dthe_hash_init_tfm, + .base.init = dthe_hash_init, + .base.update = dthe_hash_update, + .base.final = dthe_hash_final, + .base.finup = dthe_hash_finup, + .base.digest = dthe_hash_digest, + .base.export = dthe_hash_export, + .base.import = dthe_hash_import, + .base.setkey = dthe_hmac_setkey, + .base.halg = { + .digestsize = SHA384_DIGEST_SIZE, + .statesize = sizeof(struct dthe_hash_req_ctx), + .base = { + .cra_name = "hmac(sha384)", + .cra_driver_name = "hmac-sha384-dthev2", + .cra_priority = 299, + .cra_flags = CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_NEED_FALLBACK | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_FINAL_NONZERO | + CRYPTO_AHASH_ALG_FINUP_MAX | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize = SHA384_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct dthe_tfm_ctx), + .cra_reqsize = sizeof(struct dthe_hash_req_ctx), + .cra_module = THIS_MODULE, + } + }, + .op.do_one_request = dthe_hash_run, + }, + { + .base.init_tfm = dthe_hash_init_tfm, + .base.init = dthe_hash_init, + .base.update = dthe_hash_update, + .base.final = dthe_hash_final, + .base.finup = dthe_hash_finup, + .base.digest = dthe_hash_digest, + .base.export = dthe_hash_export, + .base.import = dthe_hash_import, + .base.setkey = dthe_hmac_setkey, + .base.halg = { + .digestsize = SHA256_DIGEST_SIZE, + .statesize = sizeof(struct dthe_hash_req_ctx), + .base = { + .cra_name = "hmac(sha256)", + .cra_driver_name = "hmac-sha256-dthev2", + .cra_priority = 299, + .cra_flags = CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_NEED_FALLBACK | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_FINAL_NONZERO | + CRYPTO_AHASH_ALG_FINUP_MAX | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize = SHA256_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct dthe_tfm_ctx), + .cra_reqsize = sizeof(struct dthe_hash_req_ctx), + .cra_module = THIS_MODULE, + } + }, + .op.do_one_request = dthe_hash_run, + }, + { + .base.init_tfm = dthe_hash_init_tfm, + .base.init = dthe_hash_init, + .base.update = dthe_hash_update, + .base.final = dthe_hash_final, + .base.finup = dthe_hash_finup, + .base.digest = dthe_hash_digest, + .base.export = dthe_hash_export, + .base.import = dthe_hash_import, + .base.setkey = dthe_hmac_setkey, + .base.halg = { + .digestsize = SHA224_DIGEST_SIZE, + .statesize = sizeof(struct dthe_hash_req_ctx), + .base = { + .cra_name = "hmac(sha224)", + .cra_driver_name = "hmac-sha224-dthev2", + .cra_priority = 299, + .cra_flags = CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_NEED_FALLBACK | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_FINAL_NONZERO | + CRYPTO_AHASH_ALG_FINUP_MAX | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize = SHA224_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct dthe_tfm_ctx), + .cra_reqsize = sizeof(struct dthe_hash_req_ctx), + .cra_module = THIS_MODULE, + } + }, + .op.do_one_request = dthe_hash_run, + }, + { + .base.init_tfm = dthe_hash_init_tfm, + .base.init = dthe_hash_init, + .base.update = dthe_hash_update, + .base.final = dthe_hash_final, + .base.finup = dthe_hash_finup, + .base.digest = dthe_hash_digest, + .base.export = dthe_hash_export, + .base.import = dthe_hash_import, + .base.setkey = dthe_hmac_setkey, + .base.halg = { + .digestsize = MD5_DIGEST_SIZE, + .statesize = sizeof(struct dthe_hash_req_ctx), + .base = { + .cra_name = "hmac(md5)", + .cra_driver_name = "hmac-md5-dthev2", + .cra_priority = 299, + .cra_flags = CRYPTO_ALG_TYPE_AHASH | + CRYPTO_ALG_ASYNC | + CRYPTO_ALG_NEED_FALLBACK | + CRYPTO_ALG_KERN_DRIVER_ONLY | + CRYPTO_ALG_ALLOCATES_MEMORY | + CRYPTO_AHASH_ALG_BLOCK_ONLY | + CRYPTO_AHASH_ALG_FINAL_NONZERO | + CRYPTO_AHASH_ALG_FINUP_MAX | + CRYPTO_AHASH_ALG_NO_EXPORT_CORE, + .cra_blocksize = MD5_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct dthe_tfm_ctx), + .cra_reqsize = sizeof(struct dthe_hash_req_ctx), + .cra_module = THIS_MODULE, + } + }, + .op.do_one_request = dthe_hash_run, + }, }; int dthe_register_hash_algs(void) -- 2.34.1