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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499961098cdsm157881145e9.6.2026.08.17.03.55.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Aug 2026 03:55:25 -0700 (PDT) Date: Mon, 17 Aug 2026 11:55:23 +0100 From: David Laight To: Christoph Hellwig Cc: Eric Biggers , x86@kernel.org, linux-kernel@vger.kernel.org, linux-raid@vger.kernel.org, linux-crypto@vger.kernel.org, Herbert Xu , Taehee Yoo , netfilter-devel@vger.kernel.org, Pablo Neira Ayuso , Florian Westphal , Phil Sutter Subject: Re: [PATCH 0/6] x86: add missing vzeroupper instructions Message-ID: <20260817115523.7c6c646a@pumpkin> In-Reply-To: References: <20260815205750.169336-1-ebiggers@kernel.org> <20260816161450.05fd24f2@pumpkin> <20260816173159.GB2013@sol> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Mon, 17 Aug 2026 02:15:19 -0700 Christoph Hellwig wrote: > On Sun, Aug 16, 2026 at 10:31:59AM -0700, Eric Biggers wrote: > > As for kernel_fpu_begin(), no, it doesn't do vzeroupper. > > > > I do think that some years down the line, we'll drop the use of SSE in > > the kernel entirely. At that point, vzeroupper in kernel_fpu_end() > > would make sense. > > Or add kernel_avx_{begin,end} wrappers that include the vzeroupper > in kernel_avx_end. That would be a lot easier to use than the manual > vzeroupper in every modern user of in-kernel AVX. > You might want one in the start as well. I have a theory that the avx512 logic was added as a completely separate block. This meant it could be included in cpu for testing but disabled in any released to customers. (Or maybe the it is the original avx logic that used latches not in the normal register file.) A side effect is that different latches are used for the low bits of the registers - so when you change to/from avx512 the register contents have to be transferred between the blocks - adding latency. So if the wrong registers are live for the code you are going to execute the data has to be transferred across. There are also other effects as well. I found this link: https://travisdowns.github.io/blog/2020/01/17/avxfreq1.html It is a few years old now (2020) but probably still relevant. A quick summary is that the first 256 or 512 bit instruction starts a 9us window where the cpu runs at 1/4 speed, for 512 bit that is followed by 11us where nothing happens at all. David