> -----Original Message----- > From: Linus Walleij > Sent: Monday, May 12, 2025 5:06 AM > To: Rob Herring ; Krzysztof Kozlowski > ; > Conor Dooley ; William Zhang > ; Anand Gore ; > Kursad Oney ; Florian Fainelli > ; Rafał Miłecki ; > Broadcom > internal kernel review list ; > Olivia > Mackall ; Ray Jui ; Scott Branden > ; Florian Fainelli > Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > linux- > crypto@vger.kernel.org; Linus Walleij > Subject: [PATCH v3 12/12] ARM64: dts: bcm63158: Add BCMBCA peripherals > > All the BCMBCA SoCs share a set of peripherals at 0xff800000, > albeit at slightly varying memory locations on the bus and > with varying IRQ assignments. > > Add the watchdog, GPIO blocks, RNG, LED, second UART and DMA > blocks for the BCM63158 based on the vendor files 63158_map_part.h > and 63158_intr.h from the "bcmopen-consumer" code drop. > > The DTSI file has clearly been authored for the B0 revision of > the SoC: there is an earlier A0 version, but this has > the UARTs in the legacy PERF memory space, while the B0 > has opened a new peripheral window at 0xff812000 for the > three UARTs. It also has a designated AHB peripheral area > at 0xff810000 where the DMA resides, the peripheral range > window fits these two peripheral groups. > > This SoC has up to 256 possible GPIOs due to having 8 > registers with 32 GPIOs in each available. > > Signed-off-by: Linus Walleij > --- > arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi | 129 > ++++++++++++++++++++++ > 1 file changed, 129 insertions(+) > > diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi > b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi > index > 48d618e75866452a64adfdc781ac0ea3c2eff3e8..a441388c0cd251d7dd5381f7b5 > 59633a89693232 100644 > --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi > +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi > @@ -1,6 +1,7 @@ > // SPDX-License-Identifier: (GPL-2.0+ OR MIT) > /* > * Copyright 2022 Broadcom Ltd. > + * This DTSI is for the B0 and later revision of the SoC > */ > > #include > @@ -125,6 +126,101 @@ bus@ff800000 { > #size-cells = <1>; > ranges = <0x0 0x0 0xff800000 0x800000>; > > + /* GPIOs 0 .. 31 */ > + gpio0: gpio@500 { > + compatible = "brcm,bcm6345-gpio"; > + reg = <0x500 0x04>, <0x520 0x04>; > + reg-names = "dirout", "dat"; > + gpio-controller; > + #gpio-cells = <2>; > + status = "disabled"; > + }; > + > + /* GPIOs 32 .. 63 */ > + gpio1: gpio@504 { > + compatible = "brcm,bcm6345-gpio"; > + reg = <0x504 0x04>, <0x524 0x04>; > + reg-names = "dirout", "dat"; > + gpio-controller; > + #gpio-cells = <2>; > + status = "disabled"; > + }; > + > + /* GPIOs 64 .. 95 */ > + gpio2: gpio@508 { > + compatible = "brcm,bcm6345-gpio"; > + reg = <0x508 0x04>, <0x528 0x04>; > + reg-names = "dirout", "dat"; > + gpio-controller; > + #gpio-cells = <2>; > + status = "disabled"; > + }; > + > + /* GPIOs 96 .. 127 */ > + gpio3: gpio@50c { > + compatible = "brcm,bcm6345-gpio"; > + reg = <0x50c 0x04>, <0x52c 0x04>; > + reg-names = "dirout", "dat"; > + gpio-controller; > + #gpio-cells = <2>; > + status = "disabled"; > + }; > + > + /* GPIOs 128 .. 159 */ > + gpio4: gpio@510 { > + compatible = "brcm,bcm6345-gpio"; > + reg = <0x510 0x04>, <0x530 0x04>; > + reg-names = "dirout", "dat"; > + gpio-controller; > + #gpio-cells = <2>; > + status = "disabled"; > + }; > + > + /* GPIOs 160 .. 191 */ > + gpio5: gpio@514 { > + compatible = "brcm,bcm6345-gpio"; > + reg = <0x514 0x04>, <0x534 0x04>; > + reg-names = "dirout", "dat"; > + gpio-controller; > + #gpio-cells = <2>; > + status = "disabled"; > + }; > + > + /* GPIOs 192 .. 223 */ > + gpio6: gpio@518 { > + compatible = "brcm,bcm6345-gpio"; > + reg = <0x518 0x04>, <0x538 0x04>; > + reg-names = "dirout", "dat"; > + gpio-controller; > + #gpio-cells = <2>; > + status = "disabled"; > + }; > + > + /* GPIOs 224 .. 255 */ > + gpio7: gpio@51c { > + compatible = "brcm,bcm6345-gpio"; > + reg = <0x51c 0x04>, <0x53c 0x04>; > + reg-names = "dirout", "dat"; > + gpio-controller; > + #gpio-cells = <2>; > + status = "disabled"; > + }; > + > + > + leds: led-controller@800 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "brcm,bcm63138-leds"; > + reg = <0x800 0xdc>; > + status = "disabled"; > + }; > + > + rng@b80 { > + compatible = "brcm,iproc-rng200"; > + reg = <0xb80 0x28>; > + interrupts = ; > + }; > + > hsspi: spi@1000 { > #address-cells = <1>; > #size-cells = <0>; > @@ -151,6 +247,21 @@ nandcs: nand@0 { > }; > }; > > + /* B0 AHB Peripherals */ > + pl081_dma: dma-controller@11000 { > + compatible = "arm,pl081", "arm,primecell"; > + // The magic B105F00D info is missing > + arm,primecell-periphid = <0x00041081>; > + reg = <0x11000 0x1000>; > + interrupts = ; > + memcpy-burst-size = <256>; > + memcpy-bus-width = <32>; > + clocks = <&periph_clk>; > + clock-names = "apb_pclk"; > + #dma-cells = <2>; > + }; > + > + /* B0 ARM UART Peripheral block */ > uart0: serial@12000 { > compatible = "arm,pl011", "arm,primecell"; > reg = <0x12000 0x1000>; > @@ -159,5 +270,23 @@ uart0: serial@12000 { > clock-names = "uartclk", "apb_pclk"; > status = "disabled"; > }; > + > + uart1: serial@13000 { > + compatible = "arm,pl011", "arm,primecell"; > + reg = <0x13000 0x1000>; > + interrupts = ; > + clocks = <&uart_clk>, <&uart_clk>; > + clock-names = "uartclk", "apb_pclk"; > + status = "disabled"; > + }; > + > + uart2: serial@14000 { > + compatible = "arm,pl011", "arm,primecell"; > + reg = <0x14000 0x1000>; > + interrupts = ; > + clocks = <&uart_clk>, <&uart_clk>; > + clock-names = "uartclk", "apb_pclk"; > + status = "disabled"; > + }; > }; > }; > > -- > 2.49.0 Reviewed-by: William Zhang