From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA22F2F7EE7; Tue, 1 Sep 2026 13:58:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788271104; cv=none; b=gB/4NQLU1B42/tm87Mh8JXaUGZGlQobzO+45cqI2r3jDog3+B/9BPfI/d7O43sUkBhoa5drapEOh7Hke4OwNTYvne6I7JIA4REVE8QgWHEHfZDADajJy0wPFRmqe0A0G12XNlGTPBuOdFhpRtqYLlsFRcC98KJDK2Fg2GGpavIA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788271104; c=relaxed/simple; bh=Uzb9oLzP/M/veRTwQx8O16a2XGVn4c5i03hGnQZaKic=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=pDushV396/6YifvgXeTli+tvHLt7mHIESETzRdDKkmzUJoHzXeYULzTIqHzz1QE/ulPUTZ1uQyIpUtvbV7FnM4lup9E/ywhqhe46uTz5usNC5qHfD4xB5ShGZ+C+KXAU0p/zmnWVdMEybehYBweS3q2TJERd7oX5we2X+I/m/9w= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NVxWcULt; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NVxWcULt" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D1AE61F000E9; Tue, 1 Sep 2026 13:58:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788271102; bh=v7puyWp/ROQswaeSJtWkmIdn56iY62cBg7FWAYcpIY8=; h=Date:Subject:To:Cc:References:From:In-Reply-To; b=NVxWcULtb8vZvibgQJ/A72FOUxIHYDUw2GJXZris9HtuxuyMqpwcbdSNfPO4+THil zjycOub+YLQEFzY9SEneBsrVF6ZhvhloT6Fi9bt/tJpPTGCyS9eH2AxZemWhJDpvgj CRikl0X+igBO2+zRbFVaSmAjyIQwfqEhC6jrS3RQrnqVW26Gfz2q6mOE8PGMCz+zGa oEOlXMcy+fAqIZH8tBgfE42ttP0oVYxCVa2idJK3iXtq+cZz0Dnke++ewDFtBg5jUT 5K5q1RnOa6MPc8l3SCQkLR0AQXEc8EzqDII/3nptXowzoE7r43McL55nkO3SQPEYLz WQR5IATopGGrQ== Message-ID: <38389106-9609-4ec4-bc83-3d1b7fac3698@kernel.org> Date: Tue, 1 Sep 2026 15:58:10 +0200 Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 02/11] soc: qcom: add crypto_virt backend for virtio-blk inline crypto To: Linlin Zhang , ebiggers@kernel.org, axboe@kernel.dk, mst@redhat.com, jasowangio@gmail.com, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-block@vger.kernel.org, linux-crypto@vger.kernel.org, linux-scsi@vger.kernel.org, virtualization@lists.linux.dev, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: neeraj.soni@oss.qualcomm.com, gaurav.kashyap@oss.qualcomm.com, mani@kernel.org, andersson@kernel.org, konradybcio@kernel.org, bvanassche@acm.org, alim.akhtar@samsung.com, avri.altman@sandisk.com, stefanha@redhat.com, pbonzini@redhat.com, eperezma@redhat.com, xuanzhuo@linux.alibaba.com, linux-kernel@vger.kernel.org References: <20260827160806.1295313-1-linlin.zhang@oss.qualcomm.com> <20260827160806.1295313-3-linlin.zhang@oss.qualcomm.com> <03097984-fded-477e-82b6-f9b31fd2f1d3@oss.qualcomm.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 01/09/2026 11:39, Linlin Zhang wrote: > > > On 8/31/2026 2:56 PM, Krzysztof Kozlowski wrote: >> On 27/08/2026 18:07, Linlin Zhang wrote: >>> From: linlzhan >>> >>> In a Qualcomm GVM environment the ICE hardware is controlled by the >> >> What is GVM? There is no such TLA (git grep). Maybe you meant guest in a virtual machine? Don't use some qcom-specific TLA. >> > > GVM means Guest Virtual Machine. This is designed for the virtualization > platform. > >>> host, GVM has no direct access to it. So, key operation in GVM is >>> done through SCM calls rather than direct register access. In this >>> way the access to ICE registers are offloaded to Trust Zone. >>> >>> Add QCOM_CRYPTO_VIRT, which implements struct virtblk_crypto_variant_ops >>> for the virtio_blk_crypto_ext dispatch layer. It maps keyslot >>> program/evict to qcom_scm_ice_set_key() and >>> qcom_scm_ice_invalidate_key(), and software-secret derivation to >>> qcom_scm_derive_sw_secret(). >>> >>> Signed-off-by: linlzhan >>> --- >>> drivers/soc/qcom/Kconfig | 12 +++++ >>> drivers/soc/qcom/Makefile | 1 + >>> drivers/soc/qcom/crypto_virt.c | 89 ++++++++++++++++++++++++++++++++++ >>> 3 files changed, 102 insertions(+) >>> create mode 100644 drivers/soc/qcom/crypto_virt.c >>> >>> diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig >>> index 2b524154d9fb..6c632d114d45 100644 >>> --- a/drivers/soc/qcom/Kconfig >>> +++ b/drivers/soc/qcom/Kconfig >>> @@ -298,6 +298,18 @@ config QCOM_INLINE_CRYPTO_ENGINE >>> tristate >>> select QCOM_SCM >>> >>> +config QCOM_CRYPTO_VIRT >>> + tristate "Qualcomm Technologies, Inc. Crypto Virt driver" >>> + depends on VIRTBLK_CRYPTO_VIRTUALIZATION >>> + depends on QCOM_SCM >>> + default VIRTBLK_CRYPTO_VIRTUALIZATION if ARCH_QCOM >>> + help >>> + GVM-side hardware-wrapped-key SCM operations exposed to >>> + virtio_blk's inline crypto layer: per-slot key programming and >>> + eviction, and key derive/generate/prepare/import. >>> + Say Y here to compile the driver as a part of kernel or M to compile >>> + as a module. >>> + >>> config QCOM_KRYO_L2_ACCESSORS >>> bool >>> depends on ARM64 >>> diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile >>> index 798643be3590..6d4b7546d1fb 100644 >>> --- a/drivers/soc/qcom/Makefile >>> +++ b/drivers/soc/qcom/Makefile >>> @@ -39,5 +39,6 @@ obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) += kryo-l2-accessors.o >>> obj-$(CONFIG_QCOM_ICC_BWMON) += icc-bwmon.o >>> qcom_ice-objs += ice.o >>> obj-$(CONFIG_QCOM_INLINE_CRYPTO_ENGINE) += qcom_ice.o >>> +obj-$(CONFIG_QCOM_CRYPTO_VIRT) += crypto_virt.o >>> obj-$(CONFIG_QCOM_PBS) += qcom-pbs.o >>> obj-$(CONFIG_QCOM_UBWC_CONFIG) += ubwc_config.o >>> diff --git a/drivers/soc/qcom/crypto_virt.c b/drivers/soc/qcom/crypto_virt.c >>> new file mode 100644 >>> index 000000000000..4ee2a36af6c1 >>> --- /dev/null >>> +++ b/drivers/soc/qcom/crypto_virt.c >>> @@ -0,0 +1,89 @@ >>> +// SPDX-License-Identifier: GPL-2.0-only >>> + >>> +#include >>> +#include >>> +#include >>> +#include >>> +#include >>> + >>> +static int crypto_virt_program_key(const struct blk_crypto_key *key, >>> + unsigned int slot) >>> +{ >>> + u32 dus_512_units; >>> + int ret; >>> + >>> + if (!key || !key->size) { >>> + pr_err("%s: invalid key\n", __func__); >>> + return -EINVAL; >>> + } >>> + >>> + /* Only AES-256-XTS has been tested so far. */ >>> + if (key->crypto_cfg.crypto_mode != >>> + BLK_ENCRYPTION_MODE_AES_256_XTS) { >>> + pr_err_ratelimited("Unsupported crypto mode: %d\n", >>> + key->crypto_cfg.crypto_mode); >>> + return -EINVAL; >>> + } >>> + >>> + /* qcom_scm_ice_set_key()'s data_unit_size is expressed in 512-byte units */ >>> + dus_512_units = key->crypto_cfg.data_unit_size / 512; >>> + >>> + ret = qcom_scm_ice_set_key(slot, key->bytes, key->size, >>> + QCOM_SCM_ICE_CIPHER_AES_256_XTS, dus_512_units); >>> + if (ret) >>> + pr_err("%s: slot=%u ret=%d\n", __func__, slot, ret); >>> + >>> + return ret; >>> +} >>> + >>> +static int crypto_virt_invalidate_key(unsigned int slot) >>> +{ >>> + int ret; >>> + >>> + ret = qcom_scm_ice_invalidate_key(slot); >>> + if (ret) >>> + pr_err("%s: slot=%u ret=%d\n", __func__, slot, ret); >>> + >>> + return ret; >>> +} >>> + >>> +static int crypto_virt_derive_sw_secret_key(const u8 *eph_key, size_t eph_key_size, >>> + u8 sw_secret[BLK_CRYPTO_SW_SECRET_SIZE]) >>> +{ >>> + int ret; >>> + >>> + ret = qcom_scm_derive_sw_secret(eph_key, eph_key_size, >>> + sw_secret, BLK_CRYPTO_SW_SECRET_SIZE); >>> + if (ret == -EIO || ret == -EINVAL) >>> + ret = -EBADMSG; /* probably invalid key */ >>> + >>> + if (ret) >>> + pr_err("%s: ret=%d\n", __func__, ret); >>> + >>> + return ret; >>> +} >>> + >>> +static struct virtblk_crypto_variant_ops virtblk_crypto_qcom_vops = { >> >> Why is a crypto-handling code in drivers/soc/? >> > > This driver is a Qualcomm vendor-specific driver, plays the similar role in the Not really, there is nothing vendor specific here. Look at this code. > guest, like the ice driver in the host. so I place it in drivers/soc/. > >>> + .owner = THIS_MODULE, >>> + .program_key = crypto_virt_program_key, >>> + .evict_key = crypto_virt_invalidate_key, >>> + .derive_sw_secret_key = crypto_virt_derive_sw_secret_key, >>> +}; >>> + >>> +static int __init crypto_virt_init(void) >>> +{ >>> + virtblk_set_crypto_ops(&virtblk_crypto_qcom_vops); >>> + return 0; >>> +} >>> +module_init(crypto_virt_init); >>> + >>> +#if IS_MODULE(CONFIG_QCOM_CRYPTO_VIRT) >>> +static void __exit crypto_virt_exit(void) >>> +{ >>> + virtblk_set_crypto_ops(NULL); >>> +} >>> +module_exit(crypto_virt_exit); >>> +#endif >> >> How do you instantiate this driver exactly? >> > > This driver is not instantiated per device. It acts as a provider of > Qualcomm vendor-specific inline crypto operations, which is based on > qcom_scm driver, and registers a global virtblk_crypto_ops instance > during module initialization. So that, each blk_crypto_ll_ops from > virtio block driver in common kernel can be sent via qcom_smc driver. If it is not instantiated, then it is dead code. Drop all this. Or read my message again very carefully instead of replying with whatever copy of commit msg. I did not ask what is this driver about. I did not ask what it is providing. I asked how do you instantiate it or clarifying - how do you load and run this code in final system. This is just dead/unused code, straight from downstream. NAK. Best regards, Krzysztof