[PATCH 0/5] Add separate ICE UFS and eMMC device nodes for QCS615 platform

[PATCH 0/5] Add separate ICE UFS and eMMC device nodes for QCS615 platform

[Abhinaba Rakshit]

This patch series introduces support for representing the Inline Crypto Engine (ICE)
as separate device nodes for both UFS and eMMC on the QCS615 platform.
Previously, ICE functionality was implicitly tied to the UFS/eMMC controllers.
With this update, ICE is modeled as an independent hardware block, allowing its
clock and frequency configuration to be managed directly by the ICE driver.
This separation improves modularity, aligns with hardware architecture.

The change allows the MMC/UFS controller to link to the ICE node for
crypto operations without embedding ICE-specific properties directly
in the MMC nodes.

Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
---
Abhinaba Rakshit (5):
      dt-bindings: mmc: add qcom,ice phandle to mmc
      dt-bindings: crypto: ice: add freq-table-hz property to ICE schema
      dt-bindings: crypto: ice: document the qcs615 inline crypto engine
      arm64: dts: qcom: qcs615: add ufs and emmc inline crypto engine nodes
      dts: qcom: qcs615-ride: Enable ice ufs and emmc

 .../bindings/crypto/qcom,inline-crypto-engine.yaml |  7 +++
 .../devicetree/bindings/mmc/sdhci-msm.yaml         |  4 ++
 arch/arm64/boot/dts/qcom/qcs615-ride.dts           |  8 ++++
 arch/arm64/boot/dts/qcom/sm6150.dtsi               | 51 +++++++++++++---------
 4 files changed, 49 insertions(+), 21 deletions(-)
---
base-commit: 47a8d4b89844f5974f634b4189a39d5ccbacd81c
change-id: 20251006-add-separate-ice-ufs-and-emmc-device-nodes-for-qcs615-platform-83ebc37bdddc

Best regards,
-- 
Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>

[PATCH 1/5] dt-bindings: mmc: add qcom,ice phandle to mmc

[Abhinaba Rakshit]

Add the 'qcom,ice' phandle to the MMC device tree binding to support
reference to an Inline Crypto Engine (ICE) device node.

ICE hardware is now represented as a separate device node, and its
clock and frequency configuration are managed independently by
the ICE driver.

Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
index 594bd174ff211e1bb262ad8d8c7fe1c77f1e7170..9d6be27b43cdfb349a1dc96a6687b5863af844d7 100644
--- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
+++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
@@ -138,6 +138,10 @@ properties:
     $ref: /schemas/types.yaml#/definitions/uint32
     description: platform specific settings for DLL_CONFIG reg.
 
+  qcom,ice:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: phandle to the Inline Crypto Engine node
+
   iommus:
     minItems: 1
     maxItems: 8

-- 
2.34.1

[PATCH 2/5] dt-bindings: crypto: ice: add freq-table-hz property to ICE schema

[Abhinaba Rakshit]

Introduce the 'freq-table-hz' property to specify the minimum and maximum
frequencies supported by the Inline Crypto Engine (ICE) clock.

This property is added to the ICE device node because the ICE clock is
managed independently by the ICE driver and requires frequency information
to be available in the device tree for the proper configuration.

Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
---
 .../devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml       | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
index 08fe6a707a3714ff11d01b36afc8a2aab1ad490c..88bef1d38013fc7d0e6842e370b2adb3bf3e8735 100644
--- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
@@ -29,6 +29,11 @@ properties:
   clocks:
     maxItems: 1
 
+  freq-table-hz:
+    items:
+      - description: Minimum frequency for ICE core clock in Hz
+      - description: Maximum frequency for ICE core clock in Hz
+
 required:
   - compatible
   - reg
@@ -45,5 +50,6 @@ examples:
                    "qcom,inline-crypto-engine";
       reg = <0x01d88000 0x8000>;
       clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+      freq-table-hz = <75000000 300000000>;
     };
 ...

-- 
2.34.1

[PATCH 3/5] dt-bindings: crypto: ice: document the qcs615 inline crypto engine

[Abhinaba Rakshit]

Add the compatible string for QCom ICE on qcs615 SoCs.

Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
index 88bef1d38013fc7d0e6842e370b2adb3bf3e8735..ea335d55070f0931ecf39427c59e2dfb7728cbbf 100644
--- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
@@ -13,6 +13,7 @@ properties:
   compatible:
     items:
       - enum:
+          - qcom,qcs615-inline-crypto-engine
           - qcom,qcs8300-inline-crypto-engine
           - qcom,sa8775p-inline-crypto-engine
           - qcom,sc7180-inline-crypto-engine

-- 
2.34.1

[PATCH 4/5] arm64: dts: qcom: qcs615: add ufs and emmc inline crypto engine nodes

[Abhinaba Rakshit]

Add separate ICE nodes for eMMC and UFS for QCS615 platform.

Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm6150.dtsi | 51 +++++++++++++++++++++---------------
 1 file changed, 30 insertions(+), 21 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qcom/sm6150.dtsi
index 3d2a1cb02b628a5db7ca14bea784429be5a020f9..bc1167b86e3896b9a54290e6a55ee2fa75a48c27 100644
--- a/arch/arm64/boot/dts/qcom/sm6150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi
@@ -549,11 +549,9 @@ rng@793000 {
 		sdhc_1: mmc@7c4000 {
 			compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
 			reg = <0x0 0x007c4000 0x0 0x1000>,
-			      <0x0 0x007c5000 0x0 0x1000>,
-			      <0x0 0x007c8000 0x0 0x8000>;
+			      <0x0 0x007c5000 0x0 0x1000>;
 			reg-names = "hc",
-				    "cqhci",
-				    "ice";
+				    "cqhci";
 
 			interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
@@ -562,12 +560,10 @@ sdhc_1: mmc@7c4000 {
 
 			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
 				 <&gcc GCC_SDCC1_APPS_CLK>,
-				 <&rpmhcc RPMH_CXO_CLK>,
-				 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
+				 <&rpmhcc RPMH_CXO_CLK>;
 			clock-names = "iface",
 				      "core",
-				      "xo",
-				      "ice";
+				      "xo";
 
 			resets = <&gcc GCC_SDCC1_BCR>;
 
@@ -587,6 +583,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
 			dma-coherent;
 
 			status = "disabled";
+			qcom,ice = <&ice_mmc>;
 
 			sdhc1_opp_table: opp-table {
 				compatible = "operating-points-v2";
@@ -613,6 +610,15 @@ opp-384000000 {
 			};
 		};
 
+		ice_mmc: crypto@7c8000 {
+			compatible = "qcom,qcs615-inline-crypto-engine",
+				     "qcom,inline-crypto-engine";
+			reg = <0x0 0x7c8000 0x0 0x8000>;
+			clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>;
+			freq-table-hz = <75000000 300000000>;
+			status = "disabled";
+		};
+
 		gpi_dma0: dma-controller@800000  {
 			compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma";
 			reg = <0x0 0x800000 0x0 0x60000>;
@@ -1249,10 +1255,8 @@ pcie_phy: phy@1c0e000 {
 
 		ufs_mem_hc: ufshc@1d84000 {
 			compatible = "qcom,qcs615-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
-			reg = <0x0 0x01d84000 0x0 0x3000>,
-			      <0x0 0x01d90000 0x0 0x8000>;
-			reg-names = "std",
-				    "ice";
+			reg = <0x0 0x01d84000 0x0 0x3000>;
+			reg-names = "std";
 
 			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
 
@@ -1260,7 +1264,6 @@ ufs_mem_hc: ufshc@1d84000 {
 				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
 				 <&gcc GCC_UFS_PHY_AHB_CLK>,
 				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
-				 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
 				 <&rpmhcc RPMH_CXO_CLK>,
 				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
 				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
@@ -1270,8 +1273,7 @@ ufs_mem_hc: ufshc@1d84000 {
 				      "core_clk_unipro",
 				      "ref_clk",
 				      "tx_lane0_sync_clk",
-				      "rx_lane0_sync_clk",
-				      "ice_core_clk";
+				      "rx_lane0_sync_clk";
 
 			resets = <&gcc GCC_UFS_PHY_BCR>;
 			reset-names = "rst";
@@ -1297,6 +1299,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
 			#reset-cells = <1>;
 
 			status = "disabled";
+			qcom,ice = <&ice>;
 
 			ufs_opp_table: opp-table {
 				compatible = "operating-points-v2";
@@ -1308,8 +1311,7 @@ opp-50000000 {
 						 /bits/ 64 <37500000>,
 						 /bits/ 64 <0>,
 						 /bits/ 64 <0>,
-						 /bits/ 64 <0>,
-						 /bits/ 64 <75000000>;
+						 /bits/ 64 <0>;
 					required-opps = <&rpmhpd_opp_low_svs>;
 				};
 
@@ -1320,8 +1322,7 @@ opp-100000000 {
 						 /bits/ 64 <75000000>,
 						 /bits/ 64 <0>,
 						 /bits/ 64 <0>,
-						 /bits/ 64 <0>,
-						 /bits/ 64 <150000000>;
+						 /bits/ 64 <0>;
 					required-opps = <&rpmhpd_opp_svs>;
 				};
 
@@ -1332,8 +1333,7 @@ opp-200000000 {
 						 /bits/ 64 <150000000>,
 						 /bits/ 64 <0>,
 						 /bits/ 64 <0>,
-						 /bits/ 64 <0>,
-						 /bits/ 64 <300000000>;
+						 /bits/ 64 <0>;
 					required-opps = <&rpmhpd_opp_nom>;
 				};
 			};
@@ -1360,6 +1360,15 @@ ufs_mem_phy: phy@1d87000 {
 			status = "disabled";
 		};
 
+		ice: crypto@1d90000 {
+			compatible = "qcom,qcs615-inline-crypto-engine",
+				     "qcom,inline-crypto-engine";
+			reg = <0x0 0x01d90000 0x0 0x8000>;
+			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+			freq-table-hz = <75000000 300000000>;
+			status = "disabled";
+		};
+
 		cryptobam: dma-controller@1dc4000 {
 			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
 			reg = <0x0 0x01dc4000 0x0 0x24000>;

-- 
2.34.1

[PATCH 5/5] dts: qcom: qcs615-ride: Enable ice ufs and emmc

[Abhinaba Rakshit]

Enable ICE UFS and eMMC for QCS615-ride platform.

Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/qcs615-ride.dts | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
index 705ea71b07a10aea82b5789e8ab9f757683f678a..6e80951c4159fd1fee2f737e0b271a9abaf82a49 100644
--- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
+++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
@@ -288,6 +288,14 @@ vreg_l17a: ldo17 {
 	};
 };
 
+&ice {
+	status = "okay";
+};
+
+&ice_mmc {
+	status = "okay";
+};
+
 &pcie {
 	perst-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
 	wake-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>;

-- 
2.34.1

Re: [PATCH 1/5] dt-bindings: mmc: add qcom,ice phandle to mmc

[Krzysztof Kozlowski]

On 09/10/2025 15:18, Abhinaba Rakshit wrote:
> Add the 'qcom,ice' phandle to the MMC device tree binding to support
> reference to an Inline Crypto Engine (ICE) device node.
> 
> ICE hardware is now represented as a separate device node, and its
> clock and frequency configuration are managed independently by
> the ICE driver.
> 
> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
> ---
>  Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 4 ++++
>  1 file changed, 4 insertions(+)

It is duplicating the ICE address space, so you need the same code as
other existing bindings.

Best regards,
Krzysztof

Re: [PATCH 2/5] dt-bindings: crypto: ice: add freq-table-hz property to ICE schema

[Krzysztof Kozlowski]

On 09/10/2025 15:18, Abhinaba Rakshit wrote:
> Introduce the 'freq-table-hz' property to specify the minimum and maximum
> frequencies supported by the Inline Crypto Engine (ICE) clock.
> 
> This property is added to the ICE device node because the ICE clock is
> managed independently by the ICE driver and requires frequency information
> to be available in the device tree for the proper configuration.
> 
> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
> ---
>  .../devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml       | 6 ++++++
>  1 file changed, 6 insertions(+)

This duplicates opp-table. Use OPPs instead.

Also, minimum and maximum frequencies are defined by compatible, no?

Best regards,
Krzysztof

Re: [PATCH 4/5] arm64: dts: qcom: qcs615: add ufs and emmc inline crypto engine nodes

[Krzysztof Kozlowski]

On 09/10/2025 15:18, Abhinaba Rakshit wrote:
> Add separate ICE nodes for eMMC and UFS for QCS615 platform.
> 
> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/sm6150.dtsi | 51 +++++++++++++++++++++---------------
>  1 file changed, 30 insertions(+), 21 deletions(-)


This is non-bisectable - breaks ICE on users.


Best regards,
Krzysztof

Re: [PATCH 5/5] dts: qcom: qcs615-ride: Enable ice ufs and emmc

[Krzysztof Kozlowski]

On 09/10/2025 15:18, Abhinaba Rakshit wrote:
> Enable ICE UFS and eMMC for QCS615-ride platform.
> 
> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>


Use consistent subject prefixes.

Please use subject prefixes matching the subsystem. You can get them for
example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
your patch is touching. For bindings, the preferred subjects are
explained here:
https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters

Best regards,
Krzysztof

Re: [PATCH 0/5] Add separate ICE UFS and eMMC device nodes for QCS615 platform

[Rob Herring (Arm)]

On Thu, 09 Oct 2025 11:48:50 +0530, Abhinaba Rakshit wrote:
> This patch series introduces support for representing the Inline Crypto Engine (ICE)
> as separate device nodes for both UFS and eMMC on the QCS615 platform.
> Previously, ICE functionality was implicitly tied to the UFS/eMMC controllers.
> With this update, ICE is modeled as an independent hardware block, allowing its
> clock and frequency configuration to be managed directly by the ICE driver.
> This separation improves modularity, aligns with hardware architecture.
> 
> The change allows the MMC/UFS controller to link to the ICE node for
> crypto operations without embedding ICE-specific properties directly
> in the MMC nodes.
> 
> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
> ---
> Abhinaba Rakshit (5):
>       dt-bindings: mmc: add qcom,ice phandle to mmc
>       dt-bindings: crypto: ice: add freq-table-hz property to ICE schema
>       dt-bindings: crypto: ice: document the qcs615 inline crypto engine
>       arm64: dts: qcom: qcs615: add ufs and emmc inline crypto engine nodes
>       dts: qcom: qcs615-ride: Enable ice ufs and emmc
> 
>  .../bindings/crypto/qcom,inline-crypto-engine.yaml |  7 +++
>  .../devicetree/bindings/mmc/sdhci-msm.yaml         |  4 ++
>  arch/arm64/boot/dts/qcom/qcs615-ride.dts           |  8 ++++
>  arch/arm64/boot/dts/qcom/sm6150.dtsi               | 51 +++++++++++++---------
>  4 files changed, 49 insertions(+), 21 deletions(-)
> ---
> base-commit: 47a8d4b89844f5974f634b4189a39d5ccbacd81c
> change-id: 20251006-add-separate-ice-ufs-and-emmc-device-nodes-for-qcs615-platform-83ebc37bdddc
> 
> Best regards,
> --
> Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


This patch series was applied (using b4) to base:
 Base: 47a8d4b89844f5974f634b4189a39d5ccbacd81c (use --merge-base to override)

If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)

New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/qcom/' for 20251009-add-separate-ice-ufs-and-emmc-device-nodes-for-qcs615-platform-v1-0-2a34d8d03c72@oss.qualcomm.com:

arch/arm64/boot/dts/qcom/qcs615-ride.dtb: ufshc@1d84000 (qcom,qcs615-ufshc): clock-names: ['core_clk', 'bus_aggr_clk', 'iface_clk', 'core_clk_unipro', 'ref_clk', 'tx_lane0_sync_clk', 'rx_lane0_sync_clk'] is too short
	from schema $id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#
arch/arm64/boot/dts/qcom/qcs615-ride.dtb: ufshc@1d84000 (qcom,qcs615-ufshc): clocks: [[46, 126], [46, 10], [46, 125], [46, 134], [44, 0], [46, 133], [46, 132]] is too short
	from schema $id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#
arch/arm64/boot/dts/qcom/qcs615-ride.dtb: ufshc@1d84000 (qcom,qcs615-ufshc): reg: [[0, 30949376, 0, 12288]] is too short
	from schema $id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#
arch/arm64/boot/dts/qcom/qcs615-ride.dtb: ufshc@1d84000 (qcom,qcs615-ufshc): reg-names: ['std'] is too short
	from schema $id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#
arch/arm64/boot/dts/qcom/qcs615-ride.dtb: ufshc@1d84000 (qcom,qcs615-ufshc): reg-names: ['std'] is too short
	from schema $id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#
arch/arm64/boot/dts/qcom/qcs615-ride.dtb: ufshc@1d84000 (qcom,qcs615-ufshc): Unevaluated properties are not allowed ('reg-names' was unexpected)
	from schema $id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#

Re: [PATCH 4/5] arm64: dts: qcom: qcs615: add ufs and emmc inline crypto engine nodes

[Konrad Dybcio]

On 10/9/25 8:18 AM, Abhinaba Rakshit wrote:
> Add separate ICE nodes for eMMC and UFS for QCS615 platform.
> 
> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
> ---

The commit message lacks a problem statement

Konrad

Re: [PATCH 5/5] dts: qcom: qcs615-ride: Enable ice ufs and emmc

[Konrad Dybcio]

On 10/9/25 8:18 AM, Abhinaba Rakshit wrote:
> Enable ICE UFS and eMMC for QCS615-ride platform.
> 
> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
> ---

Is there a reason to disable them in the first place?

Konrad