From: Eric Biggers <ebiggers@kernel.org>
To: Megha Dey <megha.dey@intel.com>
Cc: herbert@gondor.apana.org.au, davem@davemloft.net,
linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org,
ravi.v.shankar@intel.com, tim.c.chen@intel.com,
andi.kleen@intel.com, dave.hansen@intel.com,
wajdi.k.feghali@intel.com, greg.b.tucker@intel.com,
robert.a.kasten@intel.com, rajendrakumar.chinnaiyan@intel.com,
tomasz.kantecki@intel.com, ryan.d.saffores@intel.com,
ilya.albrekht@intel.com, kyung.min.park@intel.com,
tony.luck@intel.com, ira.weiny@intel.com, x86@kernel.org
Subject: Re: [RFC V1 0/7] Introduce AVX512 optimized crypto algorithms
Date: Mon, 21 Dec 2020 15:20:50 -0800 [thread overview]
Message-ID: <X+Et0ubPcBVZOURL@sol.localdomain> (raw)
In-Reply-To: <1608325864-4033-1-git-send-email-megha.dey@intel.com>
On Fri, Dec 18, 2020 at 01:10:57PM -0800, Megha Dey wrote:
> Optimize crypto algorithms using VPCLMULQDQ and VAES AVX512 instructions
> (first implemented on Intel's Icelake client and Xeon CPUs).
>
> These algorithms take advantage of the AVX512 registers to keep the CPU
> busy and increase memory bandwidth utilization. They provide substantial
> (2-10x) improvements over existing crypto algorithms when update data size
> is greater than 128 bytes and do not have any significant impact when used
> on small amounts of data.
>
> However, these algorithms may also incur a frequency penalty and cause
> collateral damage to other workloads running on the same core(co-scheduled
> threads). These frequency drops are also known as bin drops where 1 bin
> drop is around 100MHz. With the SpecCPU and ffmpeg benchmark, a 0-1 bin
> drop(0-100MHz) is observed on Icelake desktop and 0-2 bin drops (0-200Mhz)
> are observed on the Icelake server.
>
Do these new algorithms all pass the self-tests, including the fuzz tests that
are enabled when CONFIG_CRYPTO_MANAGER_EXTRA_TESTS=y?
- Eric
next prev parent reply other threads:[~2020-12-21 23:22 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-18 21:10 [RFC V1 0/7] Introduce AVX512 optimized crypto algorithms Megha Dey
2020-12-18 21:10 ` [RFC V1 1/7] x86: Probe assembler capabilities for VAES and VPLCMULQDQ support Megha Dey
2021-01-16 16:54 ` Ard Biesheuvel
2021-01-20 22:38 ` Dey, Megha
2020-12-18 21:10 ` [RFC V1 2/7] crypto: crct10dif - Accelerated CRC T10 DIF with vectorized instruction Megha Dey
2021-01-16 17:00 ` Ard Biesheuvel
2021-01-20 22:46 ` Dey, Megha
2020-12-18 21:11 ` [RFC V1 3/7] crypto: ghash - Optimized GHASH computations Megha Dey
2020-12-19 17:03 ` Ard Biesheuvel
2021-01-16 0:14 ` Dey, Megha
2021-01-16 0:20 ` Dave Hansen
2021-01-16 2:04 ` Eric Biggers
2021-01-16 5:13 ` Dave Hansen
2021-01-16 16:48 ` Ard Biesheuvel
2021-01-16 1:43 ` Eric Biggers
2021-01-16 5:07 ` Dey, Megha
2020-12-18 21:11 ` [RFC V1 4/7] crypto: tcrypt - Add speed test for optimized " Megha Dey
2020-12-18 21:11 ` [RFC V1 5/7] crypto: aesni - AES CTR x86_64 "by16" AVX512 optimization Megha Dey
2021-01-16 17:03 ` Ard Biesheuvel
2021-01-20 22:46 ` Dey, Megha
2020-12-18 21:11 ` [RFC V1 6/7] crypto: aesni - fix coding style for if/else block Megha Dey
2020-12-18 21:11 ` [RFC V1 7/7] crypto: aesni - AVX512 version of AESNI-GCM using VPCLMULQDQ Megha Dey
2021-01-16 17:16 ` Ard Biesheuvel
2021-01-20 22:48 ` Dey, Megha
2020-12-21 23:20 ` Eric Biggers [this message]
2020-12-28 19:10 ` [RFC V1 0/7] Introduce AVX512 optimized crypto algorithms Dey, Megha
2021-01-16 16:52 ` Ard Biesheuvel
2021-01-16 18:35 ` Dey, Megha
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