Re: [PATCH v3 4/6] drivers: crypto: qce: common: Set data unit size to message length for AES XTS transformation

[Bjorn Andersson <bjorn.andersson@linaro.org>]

On Wed 20 Jan 12:48 CST 2021, Thara Gopinath wrote:

> Set the register REG_ENCR_XTS_DU_SIZE to cryptlen for AES XTS
> transformation. Anything else causes the engine to return back
> wrong results.
> 
> Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
> ---
>  drivers/crypto/qce/common.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/crypto/qce/common.c b/drivers/crypto/qce/common.c
> index a73db2a5637f..f7bc701a4aa2 100644
> --- a/drivers/crypto/qce/common.c
> +++ b/drivers/crypto/qce/common.c
> @@ -295,15 +295,15 @@ static void qce_xtskey(struct qce_device *qce, const u8 *enckey,
>  {
>  	u32 xtskey[QCE_MAX_CIPHER_KEY_SIZE / sizeof(u32)] = {0};
>  	unsigned int xtsklen = enckeylen / (2 * sizeof(u32));
> -	unsigned int xtsdusize;
>  
>  	qce_cpu_to_be32p_array((__be32 *)xtskey, enckey + enckeylen / 2,
>  			       enckeylen / 2);
>  	qce_write_array(qce, REG_ENCR_XTS_KEY0, xtskey, xtsklen);
>  
> -	/* xts du size 512B */
> -	xtsdusize = min_t(u32, QCE_SECTOR_SIZE, cryptlen);

I wonder if this is a hardware limitation that has gone away in the
newer chips. I am however not able to find anything about it, so I'm in
favor of merging this patch and if anyone actually uses the driver on
the older hardware we'd have to go back and quirk it somehow.

Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Regards,
Bjorn

> -	qce_write(qce, REG_ENCR_XTS_DU_SIZE, xtsdusize);
> +	/* Set data unit size to cryptlen. Anything else causes
> +	 * crypto engine to return back incorrect results.
> +	 */
> +	qce_write(qce, REG_ENCR_XTS_DU_SIZE, cryptlen);
>  }
>  
>  static int qce_setup_regs_skcipher(struct crypto_async_request *async_req,
> -- 
> 2.25.1
>