From: Bjorn Andersson <bjorn.andersson@linaro.org>
To: Thara Gopinath <thara.gopinath@linaro.org>
Cc: herbert@gondor.apana.org.au, davem@davemloft.net,
ebiggers@google.com, ardb@kernel.org, sivaprak@codeaurora.org,
linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 6/6] drivers: crypto: qce: Remove totallen and offset in qce_start
Date: Mon, 25 Jan 2021 10:34:23 -0600 [thread overview]
Message-ID: <YA7zD8EpiEUB+nLv@builder.lan> (raw)
In-Reply-To: <20210120184843.3217775-7-thara.gopinath@linaro.org>
On Wed 20 Jan 12:48 CST 2021, Thara Gopinath wrote:
> totallen is used to get the size of the data to be transformed.
> This is also available via nbytes or cryptlen in the qce_sha_reqctx
> and qce_cipher_ctx. Similarly offset convey nothing for the supported
> encryption and authentication transformations and is always 0.
> Remove these two redundant parameters in qce_start.
>
Please drop "drivers: " from $subject.
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
> Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
> ---
> drivers/crypto/qce/common.c | 17 +++++++----------
> drivers/crypto/qce/common.h | 3 +--
> drivers/crypto/qce/sha.c | 2 +-
> drivers/crypto/qce/skcipher.c | 2 +-
> 4 files changed, 10 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/crypto/qce/common.c b/drivers/crypto/qce/common.c
> index f7bc701a4aa2..dceb9579d87a 100644
> --- a/drivers/crypto/qce/common.c
> +++ b/drivers/crypto/qce/common.c
> @@ -140,8 +140,7 @@ static u32 qce_auth_cfg(unsigned long flags, u32 key_size)
> return cfg;
> }
>
> -static int qce_setup_regs_ahash(struct crypto_async_request *async_req,
> - u32 totallen, u32 offset)
> +static int qce_setup_regs_ahash(struct crypto_async_request *async_req)
> {
> struct ahash_request *req = ahash_request_cast(async_req);
> struct crypto_ahash *ahash = __crypto_ahash_cast(async_req->tfm);
> @@ -306,8 +305,7 @@ static void qce_xtskey(struct qce_device *qce, const u8 *enckey,
> qce_write(qce, REG_ENCR_XTS_DU_SIZE, cryptlen);
> }
>
> -static int qce_setup_regs_skcipher(struct crypto_async_request *async_req,
> - u32 totallen, u32 offset)
> +static int qce_setup_regs_skcipher(struct crypto_async_request *async_req)
> {
> struct skcipher_request *req = skcipher_request_cast(async_req);
> struct qce_cipher_reqctx *rctx = skcipher_request_ctx(req);
> @@ -367,7 +365,7 @@ static int qce_setup_regs_skcipher(struct crypto_async_request *async_req,
>
> qce_write(qce, REG_ENCR_SEG_CFG, encr_cfg);
> qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen);
> - qce_write(qce, REG_ENCR_SEG_START, offset & 0xffff);
> + qce_write(qce, REG_ENCR_SEG_START, 0);
>
> if (IS_CTR(flags)) {
> qce_write(qce, REG_CNTR_MASK, ~0);
> @@ -376,7 +374,7 @@ static int qce_setup_regs_skcipher(struct crypto_async_request *async_req,
> qce_write(qce, REG_CNTR_MASK2, ~0);
> }
>
> - qce_write(qce, REG_SEG_SIZE, totallen);
> + qce_write(qce, REG_SEG_SIZE, rctx->cryptlen);
>
> /* get little endianness */
> config = qce_config_reg(qce, 1);
> @@ -388,17 +386,16 @@ static int qce_setup_regs_skcipher(struct crypto_async_request *async_req,
> }
> #endif
>
> -int qce_start(struct crypto_async_request *async_req, u32 type, u32 totallen,
> - u32 offset)
> +int qce_start(struct crypto_async_request *async_req, u32 type)
> {
> switch (type) {
> #ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
> case CRYPTO_ALG_TYPE_SKCIPHER:
> - return qce_setup_regs_skcipher(async_req, totallen, offset);
> + return qce_setup_regs_skcipher(async_req);
> #endif
> #ifdef CONFIG_CRYPTO_DEV_QCE_SHA
> case CRYPTO_ALG_TYPE_AHASH:
> - return qce_setup_regs_ahash(async_req, totallen, offset);
> + return qce_setup_regs_ahash(async_req);
> #endif
> default:
> return -EINVAL;
> diff --git a/drivers/crypto/qce/common.h b/drivers/crypto/qce/common.h
> index 85ba16418a04..3bc244bcca2d 100644
> --- a/drivers/crypto/qce/common.h
> +++ b/drivers/crypto/qce/common.h
> @@ -94,7 +94,6 @@ struct qce_alg_template {
> void qce_cpu_to_be32p_array(__be32 *dst, const u8 *src, unsigned int len);
> int qce_check_status(struct qce_device *qce, u32 *status);
> void qce_get_version(struct qce_device *qce, u32 *major, u32 *minor, u32 *step);
> -int qce_start(struct crypto_async_request *async_req, u32 type, u32 totallen,
> - u32 offset);
> +int qce_start(struct crypto_async_request *async_req, u32 type);
>
> #endif /* _COMMON_H_ */
> diff --git a/drivers/crypto/qce/sha.c b/drivers/crypto/qce/sha.c
> index dd263c5e4dd8..a079e92b4e75 100644
> --- a/drivers/crypto/qce/sha.c
> +++ b/drivers/crypto/qce/sha.c
> @@ -113,7 +113,7 @@ static int qce_ahash_async_req_handle(struct crypto_async_request *async_req)
>
> qce_dma_issue_pending(&qce->dma);
>
> - ret = qce_start(async_req, tmpl->crypto_alg_type, 0, 0);
> + ret = qce_start(async_req, tmpl->crypto_alg_type);
> if (ret)
> goto error_terminate;
>
> diff --git a/drivers/crypto/qce/skcipher.c b/drivers/crypto/qce/skcipher.c
> index d78b932441ab..a93fd3fd5f1a 100644
> --- a/drivers/crypto/qce/skcipher.c
> +++ b/drivers/crypto/qce/skcipher.c
> @@ -143,7 +143,7 @@ qce_skcipher_async_req_handle(struct crypto_async_request *async_req)
>
> qce_dma_issue_pending(&qce->dma);
>
> - ret = qce_start(async_req, tmpl->crypto_alg_type, req->cryptlen, 0);
> + ret = qce_start(async_req, tmpl->crypto_alg_type);
> if (ret)
> goto error_terminate;
>
> --
> 2.25.1
>
prev parent reply other threads:[~2021-01-25 16:35 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-20 18:48 [PATCH v3 0/6] Regression fixes/clean ups in the Qualcomm crypto engine driver Thara Gopinath
2021-01-20 18:48 ` [PATCH v3 1/6] drivers: crypto: qce: sha: Restore/save ahash state with custom struct in export/import Thara Gopinath
2021-01-25 16:07 ` Bjorn Andersson
2021-02-02 23:49 ` kernel test robot
2021-01-20 18:48 ` [PATCH v3 2/6] drivers: crypto: qce: sha: Hold back a block of data to be transferred as part of final Thara Gopinath
2021-01-25 16:19 ` Bjorn Andersson
2021-01-20 18:48 ` [PATCH v3 3/6] drivers: crypto: qce: skcipher: Fix regressions found during fuzz testing Thara Gopinath
2021-01-25 16:25 ` Bjorn Andersson
2021-01-20 18:48 ` [PATCH v3 4/6] drivers: crypto: qce: common: Set data unit size to message length for AES XTS transformation Thara Gopinath
2021-01-25 16:31 ` Bjorn Andersson
2021-01-20 18:48 ` [PATCH v3 5/6] drivers: crypto: qce: Remover src_tbl from qce_cipher_reqctx Thara Gopinath
2021-01-25 16:32 ` Bjorn Andersson
2021-01-20 18:48 ` [PATCH v3 6/6] drivers: crypto: qce: Remove totallen and offset in qce_start Thara Gopinath
2021-01-25 16:34 ` Bjorn Andersson [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=YA7zD8EpiEUB+nLv@builder.lan \
--to=bjorn.andersson@linaro.org \
--cc=ardb@kernel.org \
--cc=davem@davemloft.net \
--cc=ebiggers@google.com \
--cc=herbert@gondor.apana.org.au \
--cc=linux-crypto@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=sivaprak@codeaurora.org \
--cc=thara.gopinath@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).