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[35.185.214.157]) by smtp.gmail.com with ESMTPSA id e13sm21516384pfd.11.2021.07.19.10.18.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jul 2021 10:18:37 -0700 (PDT) Date: Mon, 19 Jul 2021 17:18:33 +0000 From: Sean Christopherson To: Brijesh Singh Cc: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-efi@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-coco@lists.linux.dev, linux-mm@kvack.org, linux-crypto@vger.kernel.org, Thomas Gleixner , Ingo Molnar , Joerg Roedel , Tom Lendacky , "H. Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Andy Lutomirski , Dave Hansen , Sergio Lopez , Peter Gonda , Peter Zijlstra , Srinivas Pandruvada , David Rientjes , Dov Murik , Tobin Feldman-Fitzthum , Borislav Petkov , Michael Roth , Vlastimil Babka , tony.luck@intel.com, npmccallum@redhat.com, brijesh.ksingh@gmail.com Subject: Re: [PATCH Part2 RFC v4 25/40] KVM: SVM: Reclaim the guest pages when SEV-SNP VM terminates Message-ID: References: <20210707183616.5620-1-brijesh.singh@amd.com> <20210707183616.5620-26-brijesh.singh@amd.com> <2711d9f9-21a0-7baa-d0ff-2c0f69ca6949@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org On Mon, Jul 19, 2021, Brijesh Singh wrote: > > On 7/16/21 7:46 PM, Sean Christopherson wrote: > > > takes the page size as a parameter even though it unconditionally zeros the page > > size flag in the RMP entry for unassigned pages. > > > > A wrapper around rmpupdate() would definitely help, e.g. (though level might need > > to be an "int" to avoid a bunch of casts). > > > > int rmp_make_shared(u64 pfn, enum pg_level level); > > > > Wrappers for "private" and "firmware" would probably be helpful too. And if you > > do that, I think you can bury both "struct rmpupdate", rmpupdate(), and > > X86_TO_RMP_PG_LEVEL() in arch/x86/kernel/sev.c. snp_set_rmptable_state() might > > need some refactoring to avoid three booleans, but I guess maybe that could be > > an exception? Not sure. Anyways, was thinking something like: > > > > int rmp_make_private(u64 pfn, u64 gpa, enum pg_level level, int asid); > > int rmp_make_firmware(u64 pfn); > > > > It would consolidate a bit of code, and more importantly it would give visual > > cues to the reader, e.g. it's easy to overlook "val = {0}" meaning "make shared". > > Okay, I will add helper to make things easier. One case where we will > need to directly call the rmpupdate() is during the LAUNCH_UPDATE > command. In that case the page is private and its immutable bit is also > set. This is because the firmware makes change to the page, and we are > required to set the immutable bit before the call. Or do "int rmp_make_firmware(u64 pfn, bool immutable)"? > > And one architectural question: what prevents a malicious VMM from punching a 4k > > shared page into a 2mb private page? E.g. > > > > rmpupdate(1 << 20, [private, 2mb]); > > rmpupdate(1 << 20 + 4096, [shared, 4kb]); > > > > I don't see any checks in the pseudocode that will detect this, and presumably the > > whole point of a 2mb private RMP entry is to not have to go walk the individual > > 4kb entries on a private access. > > I believe pseudo-code is not meant to be exactly accurate and > comprehensive, but it is intended to summarize the HW behavior and > explain what can cause the different fault cases. In the real design we > may have a separate checks to catch the above issue. I just tested on > the hardware to ensure that HW correctly detects the above error > condition. However, in this case we are missing a significant check (at > least the check that the 2M region is not already assigned). I have > raised the concern with the hardware team to look into updating the APM. Thanks! While you have their ear, please emphasive the importance of the pseudocode for us software folks. It's perfectly ok to omit or gloss over microarchitectural details, but ISA pseudocode is often the source of truth for behavior that is architecturally visible.