Issues with hw crypto and random support on Niagara2

Issues with hw crypto and random support on Niagara2

[Rolf Eike Beer]

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[Resend with CC linux-crypto]

I recently upgraded my Sun T5120 the kernel to 5.19.12. The first thing I 
noticed afterwards was that the boot took nearly one hour and spewed lots of 
warnings about crng_init=0. As a workaround I did that:

# grep -n quality /usr/src/linux/drivers/char/hw_random/n2-drv.c 
770:    np->hwrng.quality = 5;

This has solved the issue for me, boot is now down to ~2min again. I wonder if 
I'm missing something obvious like another driver that I should activate?

Then I noticed that the hw crypto support from drivers/crypto/n2_core.c fails 
to load with -EINVAL. From looking at the code I think this is because 
statesize is not set for the hash algorithms, so registering the first one 
(md5) fails and nothing else is tried. I then set NUM_HASH_TMPLS to 0 so they 
were never attempted, which resulted in the second loop succeeding:

[   40.561230] n2_crypto: n2_crypto.c:v0.2 (July 28, 2011)
[   40.561361] n2_crypto: Found N2CP at /virtual-devices@100/n2cp@7
[   40.561506] n2_crypto: Registered NCS HVAPI version 2.0
[   40.562493] n2_crypto: ecb(des) alg registered
[   40.562567] n2_crypto: cbc(des) alg registered
[   40.562687] n2_crypto: cfb(des) alg registered
[   40.562760] n2_crypto: ecb(des3_ede) alg registered
[   40.562833] n2_crypto: cbc(des3_ede) alg registered
[   40.562906] n2_crypto: cfb(des3_ede) alg registered
[   40.563007] n2_crypto: ecb(aes) alg registered
[   40.563084] n2_crypto: cbc(aes) alg registered
[   40.563156] n2_crypto: ctr(aes) alg registered
[   40.563890] n2_crypto: Found NCP at /virtual-devices@100/ncp@6

Maybe someone with the knowledge about the right statesize could send a patch? 
I'm open for testing. This is probably broken for a very long time, i.e. 
8996eafdcbad149ac0f772fb1649fbb75c482a6a (kernel v4.3).

Greetings,

Eike

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Re: Issues with hw crypto and random support on Niagara2

[Corentin Labbe]

Le Wed, Oct 05, 2022 at 04:17:45PM +0200, Rolf Eike Beer a écrit :
> [Resend with CC linux-crypto]
> 
> I recently upgraded my Sun T5120 the kernel to 5.19.12. The first thing I 
> noticed afterwards was that the boot took nearly one hour and spewed lots of 
> warnings about crng_init=0. As a workaround I did that:
> 
> # grep -n quality /usr/src/linux/drivers/char/hw_random/n2-drv.c 
> 770:    np->hwrng.quality = 5;
> 
> This has solved the issue for me, boot is now down to ~2min again. I wonder if 
> I'm missing something obvious like another driver that I should activate?
> 
> Then I noticed that the hw crypto support from drivers/crypto/n2_core.c fails 
> to load with -EINVAL. From looking at the code I think this is because 
> statesize is not set for the hash algorithms, so registering the first one 
> (md5) fails and nothing else is tried. I then set NUM_HASH_TMPLS to 0 so they 
> were never attempted, which resulted in the second loop succeeding:
> 
> [   40.561230] n2_crypto: n2_crypto.c:v0.2 (July 28, 2011)
> [   40.561361] n2_crypto: Found N2CP at /virtual-devices@100/n2cp@7
> [   40.561506] n2_crypto: Registered NCS HVAPI version 2.0
> [   40.562493] n2_crypto: ecb(des) alg registered
> [   40.562567] n2_crypto: cbc(des) alg registered
> [   40.562687] n2_crypto: cfb(des) alg registered
> [   40.562760] n2_crypto: ecb(des3_ede) alg registered
> [   40.562833] n2_crypto: cbc(des3_ede) alg registered
> [   40.562906] n2_crypto: cfb(des3_ede) alg registered
> [   40.563007] n2_crypto: ecb(aes) alg registered
> [   40.563084] n2_crypto: cbc(aes) alg registered
> [   40.563156] n2_crypto: ctr(aes) alg registered
> [   40.563890] n2_crypto: Found NCP at /virtual-devices@100/ncp@6
> 
> Maybe someone with the knowledge about the right statesize could send a patch? 
> I'm open for testing. This is probably broken for a very long time, i.e. 
> 8996eafdcbad149ac0f772fb1649fbb75c482a6a (kernel v4.3).
> 
> Greetings,
> 
> Eike

Could you try the following ?
diff --git a/drivers/crypto/n2_core.c b/drivers/crypto/n2_core.c
index 31e24df18877..20d0dcd50344 100644
--- a/drivers/crypto/n2_core.c
+++ b/drivers/crypto/n2_core.c
@@ -1229,6 +1229,7 @@ struct n2_hash_tmpl {
 	const u8	*hash_init;
 	u8		hw_op_hashsz;
 	u8		digest_size;
+	u8		statesize;
 	u8		block_size;
 	u8		auth_type;
 	u8		hmac_type;
@@ -1260,6 +1261,7 @@ static const struct n2_hash_tmpl hash_tmpls[] = {
 	  .hmac_type	= AUTH_TYPE_HMAC_MD5,
 	  .hw_op_hashsz	= MD5_DIGEST_SIZE,
 	  .digest_size	= MD5_DIGEST_SIZE,
+	  .statesize	= sizeof(struct md5_state),
 	  .block_size	= MD5_HMAC_BLOCK_SIZE },
 	{ .name		= "sha1",
 	  .hash_zero	= sha1_zero_message_hash,
@@ -1268,6 +1270,7 @@ static const struct n2_hash_tmpl hash_tmpls[] = {
 	  .hmac_type	= AUTH_TYPE_HMAC_SHA1,
 	  .hw_op_hashsz	= SHA1_DIGEST_SIZE,
 	  .digest_size	= SHA1_DIGEST_SIZE,
+	  .statesize	= sizeof(struct sha1_state),
 	  .block_size	= SHA1_BLOCK_SIZE },
 	{ .name		= "sha256",
 	  .hash_zero	= sha256_zero_message_hash,
@@ -1276,6 +1279,7 @@ static const struct n2_hash_tmpl hash_tmpls[] = {
 	  .hmac_type	= AUTH_TYPE_HMAC_SHA256,
 	  .hw_op_hashsz	= SHA256_DIGEST_SIZE,
 	  .digest_size	= SHA256_DIGEST_SIZE,
+	  .statesize	= sizeof(struct sha256_state),
 	  .block_size	= SHA256_BLOCK_SIZE },
 	{ .name		= "sha224",
 	  .hash_zero	= sha224_zero_message_hash,
@@ -1284,6 +1288,7 @@ static const struct n2_hash_tmpl hash_tmpls[] = {
 	  .hmac_type	= AUTH_TYPE_RESERVED,
 	  .hw_op_hashsz	= SHA256_DIGEST_SIZE,
 	  .digest_size	= SHA224_DIGEST_SIZE,
+	  .statesize	= sizeof(struct sha256_state),
 	  .block_size	= SHA224_BLOCK_SIZE },
 };
 #define NUM_HASH_TMPLS ARRAY_SIZE(hash_tmpls)
@@ -1424,6 +1429,7 @@ static int __n2_register_one_ahash(const struct n2_hash_tmpl *tmpl)
 
 	halg = &ahash->halg;
 	halg->digestsize = tmpl->digest_size;
+	halg->statesize = tmpl->statesize;
 
 	base = &halg->base;
 	snprintf(base->cra_name, CRYPTO_MAX_ALG_NAME, "%s", tmpl->name);