Re: [PATCH 1/6] x86: move zmm exclusion list into CPU feature flag

[Ingo Molnar <mingo@kernel.org>]

* Eric Biggers <ebiggers@kernel.org> wrote:

> On Mon, Nov 25, 2024 at 09:33:46AM +0100, Ingo Molnar wrote:
> > 
> > * Eric Biggers <ebiggers@kernel.org> wrote:
> > 
> > > From: Eric Biggers <ebiggers@google.com>
> > > 
> > > Lift zmm_exclusion_list in aesni-intel_glue.c into the x86 CPU setup
> > > code, and add a new x86 CPU feature flag X86_FEATURE_PREFER_YMM that is
> > > set when the CPU is on this list.
> > > 
> > > This allows other code in arch/x86/, such as the CRC library code, to
> > > apply the same exclusion list when deciding whether to execute 256-bit
> > > or 512-bit optimized functions.
> > > 
> > > Note that full AVX512 support including zmm registers is still exposed
> > > to userspace and is still supported for in-kernel use.  This flag just
> > > indicates whether in-kernel code should prefer to use ymm registers.
> > > 
> > > Signed-off-by: Eric Biggers <ebiggers@google.com>
> > > ---
> > >  arch/x86/crypto/aesni-intel_glue.c | 22 +---------------------
> > >  arch/x86/include/asm/cpufeatures.h |  1 +
> > >  arch/x86/kernel/cpu/intel.c        | 22 ++++++++++++++++++++++
> > >  3 files changed, 24 insertions(+), 21 deletions(-)
> > 
> > Acked-by: Ingo Molnar <mingo@kernel.org>
> > 
> > I suppose you'd like to carry this in the crypto tree?
> 
> I am planning to carry CRC-related patches myself
> (https://lore.kernel.org/lkml/20241117002244.105200-12-ebiggers@kernel.org/).

Sounds good!

> 
> > 
> > > +/*
> > > + * This is a list of Intel CPUs that are known to suffer from downclocking when
> > > + * zmm registers (512-bit vectors) are used.  On these CPUs, when the kernel
> > > + * executes SIMD-optimized code such as cryptography functions or CRCs, it
> > > + * should prefer 256-bit (ymm) code to 512-bit (zmm) code.
> > > + */
> > 
> > One speling nit, could you please do:
> > 
> >   s/ymm/YMM
> >   s/zmm/ZMM
> > 
> > ... to make it consistent with how the rest of the x86 code is 
> > capitalizing the names of FPU vector register classes. Just like
> > we are capitalizing CPU and CRC properly ;-)
> > 
> 
> Will do, thanks.

Thank you!

	Ingo