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AJvYcCWrRHUxkUq+BxRoWoehx8P5/rTeHfjvhAI13Eaa4uShFvdw3Tx/o3RIMFyES4NLl0WMutDEubzcK0DrmSY=@vger.kernel.org X-Gm-Message-State: AOJu0Yzsy+oysjvluqvOeVR972q8gsWBj30g9fdlpdQLp19W1GLmq5XO dxZmthAbmdUG3hyWdu2sBuFZmrVkX13OjI5iAarb/amagyVp33fDysN5Nt2337ecu0CXIGVyp1R RDA== X-Google-Smtp-Source: AGHT+IHlHwSyxV0LTUHRGhNseRoHCYNIY6ncZEyXAVZHr/jzCGvSjE4K7i+J2dif5I4fTGdH0/RJAkcUZUM= X-Received: from pfbeh4.prod.google.com ([2002:a05:6a00:8084:b0:730:7a22:c567]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a00:4644:b0:736:9e40:13b1 with SMTP id d2e1a72fcca58-73bd12b1315mr5481503b3a.23.1744407657218; Fri, 11 Apr 2025 14:40:57 -0700 (PDT) Date: Fri, 11 Apr 2025 14:40:56 -0700 In-Reply-To: <20250410204149.2576104-10-ross.philipson@oracle.com> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250410204149.2576104-1-ross.philipson@oracle.com> <20250410204149.2576104-10-ross.philipson@oracle.com> Message-ID: Subject: Re: [PATCH v13 09/19] x86: Secure Launch kernel early boot stub From: Sean Christopherson To: Ross Philipson Cc: linux-kernel@vger.kernel.org, x86@kernel.org, linux-integrity@vger.kernel.org, linux-doc@vger.kernel.org, linux-crypto@vger.kernel.org, kexec@lists.infradead.org, linux-efi@vger.kernel.org, iommu@lists.linux.dev, dpsmith@apertussolutions.com, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, dave.hansen@linux.intel.com, ardb@kernel.org, mjg59@srcf.ucam.org, James.Bottomley@hansenpartnership.com, peterhuewe@gmx.de, jarkko@kernel.org, jgg@ziepe.ca, luto@amacapital.net, nivedita@alum.mit.edu, herbert@gondor.apana.org.au, davem@davemloft.net, corbet@lwn.net, ebiederm@xmission.com, dwmw2@infradead.org, baolu.lu@linux.intel.com, kanth.ghatraju@oracle.com, andrew.cooper3@citrix.com, trenchboot-devel@googlegroups.com Content-Type: text/plain; charset="us-ascii" On Thu, Apr 10, 2025, Ross Philipson wrote: > + /* > + * Get a pointer to the monitor location on this APs stack to test below > + * after mwait returns. Currently %esp points to just past the pushed APIC > + * ID value. > + */ > + movl %esp, %eax > + subl $(TXT_BOOT_STACK_SIZE - 4), %eax > + movl $0, (%eax) > + > + /* Clear ecx/edx so no invalid extensions or hints are passed to monitor */ > + xorl %ecx, %ecx > + xorl %edx, %edx > + > + /* > + * Arm the monitor and wait for it to be poked by he SMP bringup code. The mwait s/he/the > + * instruction can return for a number of reasons. Test to see if it returned > + * because the monitor was written to. > + */ > + monitor > + > +1: > + mfence > + mwait > + movl (%eax), %edx Why load the value into EDX? At a glance, the value is never consumed. > + testl %edx, %edx > + jz 1b This usage of MONITOR/MWAIT is flawed. The monitor needs to be re-armed in each loop, otherwise mwait will be a glorified nop. More importantly, the exit condition needs to be checked before monitor, even on the first iteration. In the (probably extremely unlikely) scenario that the write to wake the CPU arrives before MONITOR is executed, this CPU may get stuck waiting indefinitely. E.g. something like: 1: monitor cmpl (%eax), 0 jnz 2f mwait jmp 1b 2: