From: Herbert Xu <herbert@gondor.apana.org.au>
To: Bharat Bhushan <bbhushan2@marvell.com>
Cc: bbrezillon@kernel.org, schalla@marvell.com, davem@davemloft.net,
giovanni.cabiddu@intel.com, linux@treblig.org,
bharatb.linux@gmail.com, linux-crypto@vger.kernel.org,
linux-kernel@vger.kernel.org, stable@vger.kernel.org
Subject: Re: [PATCH 3/4 v2] crypto: octeontx2: Fix address alignment on CN10K A0/A1 and OcteonTX2
Date: Wed, 21 May 2025 07:04:20 +0800 [thread overview]
Message-ID: <aC0KdBdslZM8m2Ox@gondor.apana.org.au> (raw)
In-Reply-To: <20250520130737.4181994-4-bbhushan2@marvell.com>
On Tue, May 20, 2025 at 06:37:36PM +0530, Bharat Bhushan wrote:
>
> + info->in_buffer = PTR_ALIGN((u8 *)info + info_len,
> + OTX2_CPT_DPTR_RPTR_ALIGN);
Any address that's used for bidirectional or from-device DMA
needs to be aligned to ARCH_DMA_MINALIGN.
Sorry I missed this during the first round.
Cheers,
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
next prev parent reply other threads:[~2025-05-20 23:04 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-20 13:07 [PATCH 0/4 v2]crypto: octeontx2: Fix hang and address alignment issues Bharat Bhushan
2025-05-20 13:07 ` [PATCH 1/4 v2] crypto: octeontx2: add timeout for load_fvc completion poll Bharat Bhushan
2025-05-20 13:07 ` [PATCH 2/4 v2] crypto: octeontx2: Fix address alignment issue on ucode loading Bharat Bhushan
2025-05-20 23:02 ` Herbert Xu
2025-05-21 5:37 ` Bharat Bhushan
2025-05-20 13:07 ` [PATCH 3/4 v2] crypto: octeontx2: Fix address alignment on CN10K A0/A1 and OcteonTX2 Bharat Bhushan
2025-05-20 23:04 ` Herbert Xu [this message]
2025-05-21 5:38 ` Bharat Bhushan
2025-05-20 13:07 ` [PATCH 4/4 v2] crypto: octeontx2: Fix address alignment on CN10KB and CN10KA-B0 Bharat Bhushan
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