From: Herbert Xu <herbert@gondor.apana.org.au>
To: Bharat Bhushan <bbhushan2@marvell.com>
Cc: bbrezillon@kernel.org, schalla@marvell.com, davem@davemloft.net,
giovanni.cabiddu@intel.com, linux@treblig.org,
bharatb.linux@gmail.com, linux-crypto@vger.kernel.org,
linux-kernel@vger.kernel.org, stable@vger.kernel.org
Subject: Re: [PATCH 3/4 v3] crypto: octeontx2: Fix address alignment on CN10K A0/A1 and OcteonTX2
Date: Wed, 21 May 2025 19:28:19 +0800 [thread overview]
Message-ID: <aC2406qOlaI17_f3@gondor.apana.org.au> (raw)
In-Reply-To: <20250521100447.94421-4-bbhushan2@marvell.com>
On Wed, May 21, 2025 at 03:34:46PM +0530, Bharat Bhushan wrote:
>
> @@ -429,22 +431,51 @@ otx2_sg_info_create(struct pci_dev *pdev, struct otx2_cpt_req_info *req,
> return NULL;
> }
>
> - g_sz_bytes = ((req->in_cnt + 3) / 4) *
> - sizeof(struct otx2_cpt_sglist_component);
> - s_sz_bytes = ((req->out_cnt + 3) / 4) *
> - sizeof(struct otx2_cpt_sglist_component);
> + /* Allocate memory to meet below alignment requirement:
> + * ----------------------------------
> + * | struct otx2_cpt_inst_info |
> + * | (No alignment required) |
> + * | -----------------------------|
> + * | | padding for 8B alignment |
> + * |----------------------------------|
This should be updated to show that everything following this
is on an 128-byte boundary.
> + * | SG List Gather/Input memory |
> + * | Length = multiple of 32Bytes |
> + * | Alignment = 8Byte |
> + * |----------------------------------|
> + * | SG List Scatter/Output memory |
> + * | Length = multiple of 32Bytes |
> + * | Alignment = 8Byte |
> + * | (padding for below alignment) |
> + * | -----------------------------|
> + * | | padding for 32B alignment |
> + * |----------------------------------|
> + * | Result response memory |
> + * ----------------------------------
> + */
>
> - dlen = g_sz_bytes + s_sz_bytes + SG_LIST_HDR_SIZE;
> - align_dlen = ALIGN(dlen, align);
> - info_len = ALIGN(sizeof(*info), align);
> - total_mem_len = align_dlen + info_len + sizeof(union otx2_cpt_res_s);
> + info_len = sizeof(*info);
> +
> + g_len = ((req->in_cnt + 3) / 4) *
> + sizeof(struct otx2_cpt_sglist_component);
> + s_len = ((req->out_cnt + 3) / 4) *
> + sizeof(struct otx2_cpt_sglist_component);
> +
> + dlen = g_len + s_len + SG_LIST_HDR_SIZE;
> +
> + /* Allocate extra memory for SG and response address alignment */
> + total_mem_len = ALIGN(info_len, ARCH_DMA_MINALIGN) + dlen;
> + total_mem_len = ALIGN(total_mem_len, OTX2_CPT_DPTR_RPTR_ALIGN);
> + total_mem_len += (OTX2_CPT_RES_ADDR_ALIGN - 1) &
> + ~(OTX2_CPT_DPTR_RPTR_ALIGN - 1);
> + total_mem_len += sizeof(union otx2_cpt_res_s);
This calculation is wrong again. It should be:
total_mem_len = ALIGN(info_len, OTX2_CPT_DPTR_RPTR_ALIGN);
total_mem_len += (ARCH_DMA_MINALIGN - 1) &
~(OTX2_CPT_DPTR_RPTR_ALIGN - 1);
total_mem_len += ALIGN(dlen, OTX2_CPT_RES_ADDR_ALIGN);
total_mem_len += sizeof(union otx2_cpt_res_s);
Remember ALIGN may not actually give you extra memory. So if you
need to add memory for alignment padding, you will need to do it
by hand.
Cheers,
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
next prev parent reply other threads:[~2025-05-21 11:28 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-21 10:04 [PATCH 0/4 v3] crypto: octeontx2: Fix hang and address alignment issues Bharat Bhushan
2025-05-21 10:04 ` [PATCH 1/4 v3] crypto: octeontx2: add timeout for load_fvc completion poll Bharat Bhushan
2025-05-21 10:04 ` [PATCH 2/4 v3] crypto: octeontx2: Fix address alignment issue on ucode loading Bharat Bhushan
2025-05-21 10:04 ` [PATCH 3/4 v3] crypto: octeontx2: Fix address alignment on CN10K A0/A1 and OcteonTX2 Bharat Bhushan
2025-05-21 11:28 ` Herbert Xu [this message]
2025-05-22 10:08 ` Bharat Bhushan
2025-05-21 10:04 ` [PATCH 4/4 v3] crypto: octeontx2: Fix address alignment on CN10KB and CN10KA-B0 Bharat Bhushan
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