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Mon, 16 Jun 2025 15:02:37 +0000 Date: Mon, 16 Jun 2025 16:02:30 +0100 From: Giovanni Cabiddu To: Herbert Xu CC: , , , Subject: Re: [PATCH] crypto: qat - lower priority for skcipher and aead algorithms Message-ID: References: <20250613103309.22440-1-giovanni.cabiddu@intel.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: Organization: Intel Research and Development Ireland Ltd - Co. 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?nQURhHOHHTPujP4+D842GD/iMy8r95Dc8tS3IslSjv6nLNmDZr4lMQ545y6H?= =?us-ascii?Q?ZSJuGD11CopJxfl7TB48QScTs8eq/YLr+AbMAhXEW3u+Ks6+dyTJw9hz41lc?= =?us-ascii?Q?w1eFFGmdfCo+B20vhIEcGvqlFRsvhgfUBSput6wT5PLEmd1VwnTxWRTHThIv?= =?us-ascii?Q?gJKL7ALR5LSDTNQX3V34neHn+zC76R4qV+cGT7FCNbAqxob+JX78zI0V7hRb?= =?us-ascii?Q?yAUbd/+Xt3T1l8NGAzN9MNEu1jmp2L2l0lm+AcmfuoodIzWDxt07tT8cfQxh?= =?us-ascii?Q?n1K4rAyXdmh/A6/HrsS2Zbf/79arxEefHgycfXXJt40Ezd07+A98BekL/zlU?= =?us-ascii?Q?BdWM+/Aad8PxQ83ysFMwh1BwTOLpUbLdsuAzhVrkJbV4MGAR1D6Ll5+N25at?= =?us-ascii?Q?eNPwYyPPVQhumwpUVOX/W2/XP6tLRxb0avRjEbEt1XxoLxTI/WBdrjOQKuPS?= =?us-ascii?Q?MrZtL2H8Rhk4xJ4R1XPtuwsK+N8tCBh43hZpaRXMCXORAn/DClU240HbdPiA?= =?us-ascii?Q?PlZOiGNQE48OyPG/P5w8eOsJyXDLoze9QoMiut2SZLTPy6+A5Nqdzlpk3IWp?= =?us-ascii?Q?wQ7oLT0wgJV4te9ybD4cTjwZcp+fKEIBkBBVzfFyMoEoDf7qAlcHcKFyLaVo?= =?us-ascii?Q?JRSMKzW/BqhoZ7vtnyJBTwRJ4TQPQSLwS8aaCrXYpWMjU5HZK9Hs8BImVST9?= =?us-ascii?Q?HlPxJkiH9tEqz/O2QC+J6ykelHoBXzwcKvZyaWIwYixGQW/ZI7wUWPv9qUvS?= =?us-ascii?Q?iHQtprmJSIgwLLAAXfZoSgjofpT/QDyAG95bf8U3JU4PiDIdF6mTYVZWiuG2?= =?us-ascii?Q?SdvaFlc4hfpoe/m0dOFjhz2guaMBSYMqRkq0Y89693jlrpCZZWdxDb3+HTXl?= =?us-ascii?Q?ogHPc6E9Dp+ep1/qaFa9XOWQzUgzP79boHG9Bh1Z4goICVTkSu6VwhCFNKA3?= =?us-ascii?Q?X0o2MJYYSViGgRmkuFXi4rceu2X6oiT7qEz5v7tGQpvEVUvrgXhNVZenrz7N?= =?us-ascii?Q?CshFe50VUgG/xIYI3+XVp8EYvD9qCTOzaXXEOHeq3v/x5GijHZJg64AnFjWw?= =?us-ascii?Q?EiFSymeGQwfOOm0+mgmSFoF0hKYxrkLeKXFEQVH8LTfyzY9+JtpH5vt2AeTV?= =?us-ascii?Q?5E37w8cI+z+2gawMeqkzonL+MFSIk3rsqnm3+EtMPNR0AW8eiaCiueihoKZP?= =?us-ascii?Q?viWTbM/Prs8m2yzZWSBjUa0Z7p0UOocEFOHkxv2w/I+ZCMku00RQCKFm6lXm?= =?us-ascii?Q?cet+f/ocPC/B2OZEcyJXMidi3ld1PSxqYp2A+xGxcZinCBE5ddjN1smVBZGM?= =?us-ascii?Q?PuxUv9tULofbHYIxtjM6dX+d8y6wN8fXy17mBq1TnOpz2MYUC1iz44FnUGd5?= =?us-ascii?Q?JmG3EakzxQ0oMqzVcrVHKY/zda+zn8xNIy65g0jh/SU1YB4HHUBY+ZQAf14Y?= =?us-ascii?Q?6oFMkGahyWZtjPP1YNZDmhmE/mTy4npHZ70Rxf9u+rjmvk0arJXAPUZmAbM3?= =?us-ascii?Q?jmISTDbpKtAA1BsSa3Ezk6LOo44DFQXZPZUz4pId9/zmH57s9vVtIFthuRtr?= =?us-ascii?Q?A25LQPzkSNgzMPohYM3S97jJSR1ytCAWcKYOK0K4eWVbIw4EbkPs7+W2v7jI?= =?us-ascii?Q?Uw=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: ab61b8ed-f31e-45c4-99a2-08ddace6d53b X-MS-Exchange-CrossTenant-AuthSource: CY5PR11MB6366.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jun 2025 15:02:37.8888 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ZqTxRdngRmVeMpPbBvipAWTVYqbsRvoneuv2IjvQCv6urJmc8CB0YQj92Gh1UXZuQEShs18Xhz2sDFNlVke/xNN1kaSSzZnlwiGA/YOuKgc= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS4PPF178D5B043 X-OriginatorOrg: intel.com On Mon, Jun 16, 2025 at 12:18:02PM +0800, Herbert Xu wrote: > On Fri, Jun 13, 2025 at 11:32:27AM +0100, Giovanni Cabiddu wrote: > > Most kernel applications utilizing the crypto API operate synchronously > > and on small buffer sizes, therefore do not benefit from QAT acceleration. > > So what performance numbers should we be getting with QAT if the > buffer sizes were large enough? Specifically for AES128-XTS, under optimal conditions, the current generation of QAT (GEN4) can achieve approximately 12 GB/s throughput at 4KB block sizes using a single device. Systems typically include between 1 and 4 QAT devices per socket and each device contains two internal engines capable of performing that algorithm. This level of performance is observed in userspace, where it is possible to (1) batch requests to amortize MMIO overhead (e.g., multiple requests per write), (2) submit requests asynchronously, (3) use flat buffers instead of scatter-gather lists, and (4) rely on polling rather than interrupts. However, in the kernel, we are currently unable to keep the accelerator sufficiently busy. For example, using a synthetic synchronous and single threaded benchmark on a Sapphire Rapids system, with interrupts properly affinitized, I observed throughput of around 500 Mbps with 4KB buffers. Debugfs statistics (telemetry) indicated that the accelerator was utilized at only ~4%. Given this, VAES is currently the more suitable choice for kernel use cases. The patch to lower the priority of QAT's symmetric crypto algorithms reflects this practical reality. The original high priority (4001) was set when the driver was first upstreamed in 2014 and had not been revisited until now. That said, symmetric encryption support in QAT remains relevant for chained operations, where compression and encryption can be offloaded in a single request. This capability is planned for full support in GEN6 and may be backported to GEN4 if there is sufficient demand. However, there is currently no infrastructure or in-kernel user for this functionality. Regards, -- Giovanni