Re: [PATCH] crypto: qat - fix error source for QAT GEN6 transmit interface faults

[Herbert Xu <herbert@gondor.apana.org.au>]

On Wed, Sep 16, 2026 at 07:55:36AM +0000, Suman Kumar Chakraborty wrote:
> TI_CD_PAR_STS faults were being decoded under ERRSOU1, which is
> incorrect for QAT GEN6 devices. They are actually raised on ERRSOU3.
> 
> Move the handling of TI_CD_PAR_STS faults as part of the ERRSOU3 logic
> and split the status bits by their actual source:
> 
>  - Bits 0-18 (TI_INT_ERR_DEVHALT) handled when a DEVHALT is signalled
>    and are counted once as ADF_RAS_FATAL.
>  - Bit 19 (TIMISCSTS) handled separately and counted as ADF_RAS_UNCORR.
> 
> Previously, a TI_INT_ERR_DEVHALT fault also incremented ADF_RAS_UNCORR
> in addition to ADF_RAS_FATAL. Since a DEVHALT is already fatal, remove
> the redundant increment.
> 
> Bits 20-25 of TI_CD_PAR_STS are unused/reserved on QAT GEN6. Remove them
> from the mask.
> 
> Cc: stable@vger.kernel.org
> Fixes: 7f3401d0a506 ("crypto: qat - enable RAS support for GEN6 devices")
> Signed-off-by: Suman Kumar Chakraborty <suman.kumar.chakraborty@intel.com>
> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
> Reviewed-by: Ahsan Atta <ahsan.atta@intel.com>
> ---
>  .../intel/qat/qat_common/adf_gen6_ras.c       | 20 +++++++++++++---
>  .../intel/qat/qat_common/adf_gen6_ras.h       | 24 ++++++++++---------
>  2 files changed, 30 insertions(+), 14 deletions(-)

Patch applied.  Thanks.
-- 
Email: Herbert Xu <herbert@gondor.apana.org.au>
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