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Donenfeld" , Ard Biesheuvel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , linux-crypto@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Jerry Shih References: <20251202-riscv-chacha_zvkb-fp-v2-1-7bd00098c9dc@iscas.ac.cn> <20251202053119.GA1416@sol> <80cb6553-af8f-4fce-a010-dff3a33c3779@iscas.ac.cn> <20251202063103.GA100366@sol> Content-Language: en-US From: Samuel Holland In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 2025-12-09 12:58 PM, Jerry Shih wrote: > On Tue, Dec 2, 2025 at 2:32 PM Eric Biggers wrote: >> >> On Tue, Dec 02, 2025 at 02:24:46PM +0800, Vivian Wang wrote: >>> On 12/2/25 13:31, Eric Biggers wrote: >>>> On Tue, Dec 02, 2025 at 01:25:07PM +0800, Vivian Wang wrote: >>>>> In chacha_zvkb, avoid using the s0 register, which is the frame pointer, >>>>> by reallocating KEY0 to t5. This makes stack traces available if e.g. a >>>>> crash happens in chacha_zvkb. >>>>> >>>>> No frame pointer maintenence is otherwise required since this is a leaf >>>>> function. >>>> maintenence => maintenance >>>> >>> Ouch... I swear I specifically checked this before sending, but >>> apparently didn't see this. Thanks for the catch. >>> >>>>> SYM_FUNC_START(chacha_zvkb) >>>>> addi sp, sp, -96 >>>>> - sd s0, 0(sp) >>>> I know it's annoying, but would you mind also changing the 96 to 88, and >>>> decreasing all the offsets by 8, so that we don't leave a hole in the >>>> stack where s0 used to be? Likewise at the end of the function. >>> >>> No can do. Stack alignment on RISC-V is 16 bytes, and 80 won't fit. >>> >> >> Hmm, interesting. It shouldn't actually matter, since this doesn't call >> any other function, but we might as well leave it at 96 then. I don't >> think this was considered when any of the RISC-V crypto code was >> written, but fortunately this is the only one that uses the stack. >> >> Anyway, I guess I'll apply this as-is then. >> >> - Eric > > The 16-byte stack alignment is in RISC-V calling convention: > https://riscv.org/wp-content/uploads/2024/12/riscv-calling.pdf > It says: > In the standard RISC-V calling convention, the stack grows downward > and the stack pointer is always kept 16-byte aligned. Indeed, and this does matter if the code runs with IRQs enabled, as the RISC-V entry assembly assumes the kernel stack is already properly aligned. Regards, Samuel